Gate First, or Gate Last: Technologists Debate High-k – 2010-03-10 15:41:15 | Semiconductor International
David Lammers, News Editor — Semiconductor International, 3/10/2010
Archive for the ‘ Gate stack ’ Category
(03/09/2010 4:58 PM EST)
|SAN JOSE, Calif. — In a major departure, South Korea’s Samsung Electronics Co. Ltd. is reportedly exploring an alternative in high-k dielectrics: It is looking at gate-last technology, according to sources.Initially, Samsung plans to roll out a rival gate-first, high-k technology. As previously reported, the technology will be offered at the 32- and 28-nm nodes for foundry customers, which will be rolled out this year.
Some believe that gate-first is only a one-node solution. As a result, sources believe Samsung’s foundry unit is working on a gate-last technology for 22-nm. Ana Hunter, vice president of foundry services for Samsung Semiconductor Inc., declined to comment on reports that Samsung is looking at a gate-last technology.
If the reports are true, this would be a major departure from Samsung’s original position. The gate-first technology was developed and is now being touted by IBM Corp.’s ”fab club.” IBM, Infineon, GlobalFoundries, NEC, Samsung, ST, Toshiba and others are part of IBM’s technology alliance.
IBM, GlobalFoundries and Samsung are co-developing foundry processes and will roll out a gate-first, high-k offering this year. So far, though, IBM’s camp, which includes Advanced Micro Devices Inc. (AMD), has not rolled out a high-k/metal-gate offering.
The camp is far behind Intel Corp., which has shipped 45- and 32-nm processors based on its gate-last, high-k technology.
Except for Intel, leading-edge chip makers are struggling to switch from today’s silicon dioxide to a high-k gate insulator. Silicon dioxide as a gate dielectric is running out of gas at 45-nm, but some are pushing it to 28-nm.
But high-k has been delayed because of difficulties in developing the technology. In addition to high-k, chip makers must also move to metal gates, replacing the N and P doped polysilicon gate electrodes with metallic alloys to eliminate polysilicon depletion at the gate.
There are two basic approaches to the next-generation gate stack in logic designs. IBM’s ”fab club” is using a gate-first approach, while Intel is deploying a rival replacement-gate or gate-last technology. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.
In any case, Samsung will likely become one of the first foundries to roll out a high-k/metal-gate solution for customers. ”We think that gate-first is best suited for today’s needs,” Samsung’s Hunter said.
At the recent Semico Outlook conference, Hunter also provided six basic reasons why Samsung believes it will succeed in the foundry business.
It’s unclear if Samsung will implement gate-last at 22-nm. It has quietly assembled an R&D group that is exploring the technology. It’s also unclear if IBM’s fab club will make the switch or not.
Rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has already switched camps. Originally, TSMC was planning to go with a gate-first technology. Now, it will go with gate-last.
”The first high-k metal gate we call 28 HP for the high performance application will be introduce the end of September this year. This is the first high-k metal gate introduction for low power applications,” said Shang-Yi Chiang, senior vice president of R&D at TSMC, in a recent presentation.
”At this moment the only way we know how to do that is the gate last approach,” he said. ”This is a controversial issue in the industry. The industry (has) diverged to two approaches. One is what we call gate-first. Another is gate-last.”
Gate-last, according to TSMC, has some advantages. ”The gate-last process is a little more complicated and a lot more difficult to do. But after you learn that (process), the challenge is very much the same, and the cost is pretty much the same,” he said.
”The real key difference in the gate-last approach (is that) we use two different gate metals, one metal for the P channel and one metal for N channel. For the gate-first approach, we use the same metal for N and P channel. In gate-last, we can freely adjust voltage for both N channel and P channel. Gate-first has difficulty doing that. So that’s a major difference,” he added.
With today’s launch of the all new 2010 Intel® Core Processor Family (based on Westmere, code name for our 32nm project), this is a great time to discuss the the 32nm process technology (and the semiconductor communities response to this technology!)
Traditionally, Intel presents the details of its process technologies at the International Electron Devices meeting (IEDM) and 32nm is no exception. Although I was unable to attend the conference this year, my colleagues (and the faithful blogosphere) have provided me with an opportunity to tell the real story.
The 32nm process technology is based on high-k metal gate. Intel was the first manufacturer to introduce the high-k metal gate technology into manufacturing in 45nm (see IEDM 2007) and (as Carl Wintgens from EE times points out) “Semiconductor Insights has yet to observe a metal gate technology in a commercial device from any other semiconductor manufacturer.”
Like Intel’s 45nm technology, Intel’s 32nm high-k metal gate process is a gate-last (or replacement gate process). The gate-last (or replacement gate) architecture provides a higher thermal budget for the midsection (better activation of S/D anneals), lower thermal budget for the metals (improved range of metal choices) AND delivers significant improvement of strain for both NMOS and PMOS. The metal gate (and associated strain) gives these transistors more performance at the same power, to enable your favorite performance-hungry applications (things like games, video editing and so on).
The high-k metal gate process in 32nm generated some big headlines in the blogsphere. David Lammers of Semiconductor International reported the big news, as “Intel’s flagship 32 nm technology achieved record drive current levels, with the PMOS transistor showing a 35% drive current improvement over the 45 nm PMOS device.” Lammers also picked up a subtle but key aspect of 32nm as he pointed out “For the first time, linear drive currents on the PMOS have overtaken NMOS.” It will only be a short time before saturated drive currents on PMOS overtake NMOS (perhaps at 22nm?). Matched drive currents on NMOS and PMOS permit the best possible layout density (thus lower cost!) and have been a “wish-list” item from designers for decades.
There has been much discussion on gate first vs gate last (or replacement gate) since Intel’s initial introduction of replacement gate in 45nm. However, as David Lammers from Semiconductor International reports, Intel’s vision on gate last is finally being appreciated. Lammers headline says a great deal with, “Problems with the gate-first approach to high-k/metal gate deposition may force IBM to switch to the gate-last approach pioneered by Intel.” Lammers adds, “Concerns about threshold voltage shifts and other performance problems with the gate-first approach to high-k/metal gate creation may cause GlobalFoundries (Sunnyvale, Calif.) and other members of the IBM-led Fishkill Alliance to shift to a gate-last technique, sources said at the International Electron Devices Meeting (IEDM), going on this week in Baltimore [IEDM 2009].” In addition, Lammers reports, “”The baseline roadmap at TSMC is gate last,” said Jack Sun, in charge of technology strategy at TSMC.”
Of course, the most important point illustrated by 32nm is that it continues to maintain Moore’s law scaling! Carl Wintgens from EE times takes the stance that Moore’s Law is alive an well, with “All three players [i.e. Intel, AMD, TSMC] had comparable critical dimensions, illustrating that Moore’s law is alive and well with no sign of slowing.” Lammers from Semiconductor International was slightly more pessimistic with, “Though several participants at IEDM said CMOS scaling is likely to slow to a three-year pace, Bohr said Intel plans to stay on a two-year cadence.”
As a closing thought, Carl Wintgens from EE times highlights Intel’s continued commitment to driving innovation with “Intel clearly shows leadership in implementing process innovations”
For a look at the detailed IEDM technical papers showcasing these neat features, check out the links below!
32nm at IEDM 2009: Paper
32nm at IEDM 2008: Foils and Paper and David Kantor at Real World Technologies 2008 article
I’m writing this on the plane from Narita airport to Portland as I return from giving the plenary talk at the Solid State Devices and Materials conference (SSDM), in Sendai Japan. It is always exciting to visit these device conferences to see the myriad of new options that are being discussed for next generation transistors.
Before I get into the technical details, I have a few fun stories to share about my trip. I arrived a little early, so I could have the weekend to tour Tokyo. Much of my time in Tokyo was spent figuring out the subway/train system. In all the excitement, I managed to lose my wallet on the subway, and to my surprise and delight – it was returned a few hours later (with all the money intact). I was deeply impressed as I doubt that would happen in New York! Another adventure was with a Japanese toilet at Tokyo institute of technology. Japanese toilets are quite complicated (among other things, they play music) with a number of interesting features (which I will not describe here, you’ll need to go to Japan to check). This was one of the more complicated ones, and in looking for the flush button, I pushed a green button that looked reasonable. Well, it was an alarm button. A horn sounded, the lights turned on and off and so on and so on. Made me deeply suspicious of all buttons for the rest of the trip. At this point, I hoped my adventures were over, but no. I had a most interesting night on the 12th floor of the hotel when the typhoon Melor passed over (as a side note, I began to feel jinxed, because I ran into Melor a second time when in California a few days later after it had crossed the Pacific).
Anyway, enough of the light stuff, now let’s discuss the meat! SSDM is a big conference (~1000 people) where the various conference sessions include papers ranging from energy systems to organic semiconductors. Of the most interest to me were the sessions focusing on the various approaches for continued gate scaling through improved short channel control.
High-k metal gate is the primary path for improved short channel control. Intel leads the pack in this area, with its recent 32nm announcement demonstrating successful second-generation high-k metal gate (http://www.intel.com/technology/architecture-silicon/32nm/index.htm). Note that much of the industry is trying to “catch up” to Intel, with significant discussion industry-wide on the correct architecture for the gate (gate-first or replacement, one metal or two, and so on) with representative SSDM papers such as those presented by Drs. Ikeda, Kim and Fukutome. There is also significant research on gate materials, shown with papers such as those from Drs. Kadoshima and Inumiya. Another area of strong research is fundamental physics of the HiK-metal gate materials system, with SSDM papers such as those by Drs. Hsieh and Shimizu.
Advanced device architectures are another path for improved short channel control. This include ultra thin body (UTB) devices, vertical thin body devices (for example, trigate and Finfet), and lateral nanowire devices. UTB devices are the simplest of the new architectures, with short channel control offered by a thin body, and with fabrication being an extension of historical processing. An additional advantage of UTB devices is excellent random variation due to the undoped depleted body (several interesting SSDM papers in this area, including the papers of Drs. Andrieu and Lee). The problem is that UTB devices are expensive (SOI is NOT cheap), and quite sensitive to variation in the body thickness (changes in body thickness affect VT from quantum effects, and also impact DIBL and SS)). In addition, the thin body creates high external resistance and makes it extremely difficult to strain the devices.
Multiple gate (MuGFET) devices such as FinFETs or Trigates are a longer term path for improved short channel control. These devices mitigate many of the variation issues with UTB devices (because the desired fin width is greater than 2X of the equivalent body thickness in an UTB device.) HOWEVER, the non-planarity of these devices represents significant challenges in fabrication. Dr. Veloso’s paper nicely explored many of these challenges in some detail. Lateral nanowire devices are next in the logical sequence, again offering significant advantages for short channel control, but at the cost of challenging fabrication. While nanowires offer further short channel benefit, they have all the issues of FinFETs, along with a host of new issues, many of which were explored in papers from Drs. Chen, Seike, Lee and others.
I had a lot of fun, and learned some new things. As a wonderful closure for the trip, as we were leaving Narita airport (after pushback and just as the plane started to taxi on its own) all the line service folks (the people who fuel the plane etc.) lined up and waved and then bowed the plane off. “What a wonderful custom,” I thought, as I waved back.