Archive for the ‘ III-V MOSFET ’ Category

EETimes.com – Intel’s Gargini pushes III-V-on-silicon as 2015 transistor option

EETimes.com – Intel’s Gargini pushes III-V-on-silicon as 2015 transistor option.

LONDON — A presentation prepared by Paolo Gargini, Intel’s director of technology strategy, to give to the Industry Strategy Symposium Europe, held in Dublin, Ireland, earlier this week, stressed Intel’s progress in adding compound semiconductor layers to silicon as a means of continuing scaling and reducing power consumption.

Gargini, also chairman of the International Technology Roadmap for Semiconductors (ITRS), said in the presentation that the inclusion of III-V materials is a 2015 transistor option that could deliver either three times the performance of silicon at the same power consumption, or deliver the same performance as silicon at one-tenth the power consumption. However, integration of a thin compound semiconductor transistor channel with conventional silicon manufacturing would be the key to adoption.

While exceptional progress has been made in silicon to get to 32-nm, Gargini indicated in his slides that progress is coming only with more and more complicated additions to the basic silicon manufacturing process, such as the increased amounts of strain necessary to increase the electron mobility above its natural value; and the possible use of 3-D structures such as FinFETs.

Multigate FinFETs have advantages in improved electrostatics and a steeper sub-threshold slope, but Gargini put question marks against such things as parasitic resistance and capacitance and a layout methodology.

“Increase mobility in the transistor channel leads to higher performance and less energy consumption,” said Gargini on the slide, adding, “compound semiconductors have higher electron mobility than silicon; indium antimonide is highest of all.” Where gallium arsenide has 8 times higher mobility than silicon, indium arsenide is 33 times higher and indium antimonide is 50 times higher.

In the presentation Gargini laid out a few alternatives for integration. One method would be to include indium antimonide quantum-well FETs on a semi-insulating gallium arsenide substrate. Both depletion- and enhancement mode devices are possible.

As an alternative Gargini outlined progress in integrating an InGaAs quantum-well FET with a high-k dielectric gate stack. Gargini highlighted a series of papers presented by Marko Radosavljevic of Intel to the International Electron Devices Meeting (IEDM) over the years 2007 to 2009. This illustrated progress in developing the NMOS, PMOS transistors and, in December 2009, the high-K metal gate.

Gargini’s final conclusion was: “The advancement in non-silicon semiconductors deposited on silicon substrates could enable a new family of low power devices in the future.”

Technology@Intel · Doodles … and mobility enhancement

Technology@Intel · Doodles … and mobility enhancement.

Doodles … and mobility enhancement

posted by Kelin Kuhn on December 21, 2009

The Intel “Doodle” advertisement went public recently. While an actress plays me (the idea is the actress is younger, prettier and taller than I am J) the doodles are mine and capture technical highlights of various Intel projects I’ve been involved with. There has been significant curiosity about the Doodle itself and so I’ve given a couple of talks recently to “unpack” the Doodle for interested audiences (a hyperlinked version of these talks is at http://www.intel.com/pressroom/kits/advancedtech/ scroll down to the doodle and click on the pictures for a discussion of each one).

In giving these talks, I am continually reminded of the importance of mobility enhancement in Intel’s long term technical roadmap. (Remember that transistor drive current is directly proportional to mobility, and so any improvement in mobility is a 1 for 1 improvement in drive current and thus performance).

The most significant mobility enhancement technique is transistor strain. Strain was first introduced by Intel in the 90nm generation (http://download.intel.com/pressroom/kits/advancedtech/pdfs/Mark_Bohr_story_on_strained_silicon.pdf ), and its contribution to Intel’s transistor scaling roadmap has increased each generation. Intel has pioneered a number of strain techniques including CESL (strain from the contact etch-stop layer), e-SiGe (strain from including SiGe in the source/drain regions), strain directly from the contact metal, and (with HiK-metal gate) strain enhancement produced by the HiK-MG replacement gate process and strain directly from the metal gate (for key Intel papers see C. Auth at IEDM 2008, http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_VLSI2008_ppt.htm and http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_VLSI2008_doc.htm for a graphical history see K. Kuhn at IWCE 2009, http://download.intel.com/pressroom/pdf/kkuhn/Kuhn_IWCE_invited_slides.pdf starting after pg. 40).   

Another option for mobility enhancement is using a different Si substrate orientation (for example, 110 vs 100).  This is more complex than it sounds, as NMOS is better on 100 and PMOS is better on 110, and both cannot exist on the same simple (read cheap!) wafer.   A critical question with this approach is just how much the PMOS improves and the NMOS degrades – because, if the NMOS degradation is small enough, this is still worth doing (see P. Packan at IEDM 2008, http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_IEDM2008_ppt.htm and http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_IEDM2008_doc.htm ). Now, it IS possible to fabricate the NMOS transistor horizontally and the PMOS transistor vertically to get the optimal orientation in both cases. The issue here is process and design rule complexity (i.e. high cost!). Another alternative (for example, the IBM HOT process) is to integrate both crystal orientations on the same wafer. The issue here is … HIGH COST!

A longer term option is replacement of silicon by new channel materials (for example, Ge or III-V materials).   Note that while replacing the entire wafer with Ge or III-V is incompatible with modern 300mm manufacturing, replacing only the channel with Ge or III-V materials is a potentially manufacturable approach.

While Ge is a very well known semiconductor (the first transistors were made of Ge!), the concern with Ge is that its native oxide (GeO) is a poor thermally unstable oxide. A fascinating option is to make Ge transistors with HiK dielectrics rather than GeO – however, this is not a trivial challenge! Even today, there is no known method for fabricating thin (say 1nm EOT) high mobility dielectrics on Ge (literature results reporting exceptional mobilities are from thick gates). Another issue is the narrow bandgap of Ge, which increases band-to-band tunneling and results in higher standby leakage (Ioff). Still another issue is the lattice mismatch between Si and Ge; which can result in various defects and dislocations.

III-V materials are both more challenging and have more potential than Ge. As with Ge, integration of gate dielectrics is a major challenge. As with Ge, the low Eg III-V materials (ex: InAs, InSb, Ge) are subject to standby leakage (Ioff) increases due to band-to-band tunneling (and the effect worsens with strain). The very high mobility materials (ex: InAs, InSb) have low density of states in the gamma-valley, resulting in reduced drive currents. Last, but not least, III-V materials are also lattice mismatched to Si, creating various defects and dislocations. However, in spite of these challenges, Intel has recently reported integration of a composite high-k gate stack on InGaAs (see M. Radosavljevic, IEDM 2009, link pending) as well as the major milestone of improved low power performance of III-V over Si for the voltage range of 0.5-1V (see G. Dewey, IEDM 2009, link pending).

Stay tuned, next month – IEDM, 32nm and what that means for the all new 2010 Intel® Core Processor Family

Research@Intel · Enforcing Moore’s Law through Technology Research – Part 3

Research@Intel · Enforcing Moore’s Law through Technology Research – Part 3.

Enforcing Moore’s Law through Technology Research – Part 3

posted by Mike Mayberry on December 07, 2009

Welcome to the third installment! I’ve been blogging about research progress towards making compound semiconductors mainstream and talking about both challenges and opportunities.

Enforcing Moore’s Law, Part 1

Enforcing Moore’s Law, Part 2

In this blog, I’ll update the progress and give a look ahead to some of the upcoming research projects.

First as a reminder, unlike silicon, a compound semiconductor is made up of two or more elements, indium, gallium and arsenic for example (InGaAs). Using two or more elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. Today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs. Our goal is to take advantage of the vastly larger spending on silicon infrastructure and put it to use fabricating compound semiconductor devices.

I gave five individual challenges which needed to be solved in order to allow broader use of compound semiconductor technology and we are working both internally as well as with external groups such as universities to make progress on this list:

  • Build compound semiconductor devices on silicon substrates. That would allow us to reuse the highly refined silicon infrastructure including 300mm wafers and down the road gives us the option of integrating a few specialized devices with a sea of silicon devices. [progress reported at IEDM 2007]
  • Find a suitable high K gate dielectric. Due to the different surface, the silicon high K solution won’t work as is but we can leverage knowledge we gained to help guide us. [progress to be reported at IEDM 2009, Ref. 1]
  • Build a high performance PMOS device to go with the existing NMOS. This is needed to have power efficient CMOS logic though some special circuits can get by with just one type. [progress reported at IEDM 2008]
  • Build enhancement devices. Most existing work is based on depletion mode where you apply a voltage to shut them off. Power efficiency demands that those devices be normally off. [progress reported at IEDM 2007]
  • Make them small enough to compete with silicon transistor densities. If we stop at integrating only a few specialized devices then this is not needed but then we also won’t reap the full benefit of the technology.

The last blog focused on item #3, using strain to increase the mobility of the P-channel and we were able to achieve 5x mobility improvement over strained silicon by adding ~2% biaxial strain to the material. We have an upcoming paper at IEDM 2009 [Ref. 1] which reports progress on item #2, finding a suitable high-k dielectric.

Most silicon devices today are MOS (Metal Oxide Semiconductor) devices where the controlling gate electrode is separated from the conductive channel by a thin oxide layer. A thinner oxide gives greater control of the channel but also can create higher leakage as the current tunnels through the thin layer. Our implementation of high-k with metal gates allows the channel to have great control while suppressing leakage currents by up to 100x compared to a gate dielectric with the same electrical thickness. This in turn gives best in class transistor performance.

By contrast the highest performing III-V devices are not MOS devices. Generically they are quantum well field effect devices (QWFET) where the quantum well is created with a very thin (~10nm) high-mobility layer sandwiched between two high resistance barriers. Because the quantum well is undoped and its interfaces are smooth, scattering is suppressed, and charges can move very quickly.

EnforceFig1.JPG The channel is still controlled by the gate electrode (field effect) but the separation is via a Schottky contact. The reason people built gates this way is that thin oxides with the required high quality don’t natively grow on III-V surfaces. Since these are compound semiconductors, there are two or more elements at the surface and these react at different rates. What you get is a mixture of states, irregularities, and ultimately poor performing devices. However use of a Schottky contact means that when the barrier is thinned, the gate leakage current goes up exponentially.

EnforceFig2.JPG

Last year’s IEDM had a whole session devoted to fabrication of III-V MOSFET’s with high-K dielectrics and had a good mixture of both basic material science as well as engineering. There are multiple techniques for cleaning the surface of any native oxide; the trick is to then get the right dielectric down without creating interface traps. Some possibilities include 1) in situ clean + direct dielectric deposition, 2) clean + surface passivation + dielectric deposition, 3) clean + thin transition layer + dielectric deposition, and each of these has many choices for chemistry and materials. Our paper results are using technique 3, and we’ve introduced two new materials into the stack bringing up to seven unique materials in order to make it work. We also have a second paper in this year’s IEDM [Ref. 2] which benchmarks these devices against their silicon competition and shows they perform better for a range of lower voltages which translates to power savings.

Recapping the challenge list:

  • We have demonstrated we can build N channel quantum well devices on a silicon substrate with equivalent performance to those grown on III-V substrates
  • We can modulate the device operation to act as an enhancement device, not just depletion
  • We can integrate high-k dielectrics on N-channel and still get good performance
  • We can make a fast P channel device to go with the N channel device

Some work in progress:

  • These devices are still very big. While there’s been some good work to make short channels and self-alignment (e.g. at MIT), we will likely need a new device architecture to improve the density to compete with silicon

I’ll illustrate the problem with a SEM of one of our previous devices.

EnforceFig3.JPG

In this figure the gate appears as a very narrow line while all the other structures are very big. In part this is large to make it easy to measure but there are also hidden challenges to making it smaller. Creating the quantum well suppresses interactions outside the well which makes moving charges into and out of the QW harder (=high equivalent resistance). Making contacts large hides this issue. So another material challenge is to engineer a contact structure which minimizes the barrier between the metallic contact and the QW. A second challenge is to predict/measure what happens when the device becomes small in three dimensions. This is still a classical device but there are strong quantum-mechanical effects that need to be considered.

If we can make all of the material integration challenges happen and also make dense devices then III-V technology could replace silicon technology starting around the middle of the next decade. There is still much work to be done to achieve this but stay tuned for further progress.

Ref. 1: M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah, and R. Chau, “Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications”.

Ref. 2: G. Dewey, R. Kotlyar, R. Pillarisetty, M. Radosavljevic, T. Rakshit, H. Then, and R. Chau, “Logic Performance Evaluation and Transport Physics of Schottky-Gate III-V Compound Semiconductor Quantum Well Field Effect Transistors for Power Supply Voltages (VCC) Ranging from 0.5V to 1.0V”.

Research@Intel · Enforcing Moore’s Law through Technology Research – Part 2 with Mike Mayberry

Research@Intel · Enforcing Moore’s Law through Technology Research – Part 2 with Mike Mayberry.

Enforcing Moore’s Law through Technology Research – Part 2 with Mike Mayberry

posted by Mike Mayberry on September 15, 2008

Last summer I wrote about compound semiconductors, both challenges and opportunities.

In this blog, I’ll update the progress and give a look ahead to some of the potential paths for use. First as a reminder, unlike silicon, a compound semiconductor is made up of two or more elements, indium, gallium and arsenic for example (InGaAs). Using two or more elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. Today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs.

I gave five individual challenges which needed to be solved in order to allow broader use of compound semiconductor technology and we are working both in internally as well as with external groups such as universities to make progress on this list:

  • Build compound semiconductor devices on silicon substrates. That would allow us to reuse the highly refined silicon infrastructure including 300mm wafers and down the road gives us the option of integrating a few specialized devices with a sea of silicon devices. [progress reported at IEDM 2007]
  • Find a suitable high K gate dielectric. Due to the different surface, the silicon high K solution won’t work as is but we can leverage knowledge we gained to help guide us.
  • Build a high performance PMOS device to go with the existing NMOS. This is needed to have power efficient CMOS logic though some special circuits can get by with just one type.
  • Build enhancement devices. Most existing work is based on depletion mode where you apply a voltage to shut them off. Power efficiency demands that those devices be normally off. [progress reported at IEDM 2007]
  • Make them small enough to compete with silicon transistor densities. If we stop at integrating only a few specialized devices then this is not needed but then we also won’t reap the full benefit of the technology.

The last blog focused on item #1, fabricating III-V devices on silicon substrates. Stated another way, what we are after is leveraging the orders of magnitude higher spending on silicon process tools and factories so that there is a much lower hurdle to introduce the technology. Items #3 and #4 on the list similarly drive leveraging silicon design tools and for this blog I’ll focus on item #3, building a high performance P channel device to go with the N channel.

Today’s silicon technology is based on CMOS (Complementary Metal Oxide Semiconductor) but it hasn’t always been that way. Past silicon generations included NMOS or PMOS where the N and P refer the charge of the carrier within the channel (negative or positive). With those technologies we eventually hit a power wall and then Moore’s Law scaling continued with new CMOS technology. The C means complementary and in a typical circuit the N channel device is back to back with a P channel device. That configuration means one device is on while other off and CMOS is much better for static power than either NMOS or PMOS alone. In an ideal world we would figure out how to make CMOS III-V’s or at least be able to copy the beneficial attributes of complementary devices.

Most research on III-V materials and devices has focused on N channel because the mobility of the electrons (negative) is much higher than that of holes (positive). Higher mobility means less voltage is required to move the charge and in turn you get a higher performance device. A typical N channel example is shown here where a 30x higher electron mobility translates to a 10x improvement in relative power vs performance.

RelativeMobility1.png

RelativePower2.png

Unfortunately holes have 20-100x worse mobility for most III-V materials contrasted with silicon which has only about 3x difference. If you aim to write a research paper, it is a lot more rewarding to write about the fast N channel and neglect the P.

We can make the P mobility higher by copying a technique from silicon processing, add strain to the material. Strain works by changing the band structure to favor a population of light holes instead of the mixture of heavy and light holes in unstrained material. In silicon, our leading edge processes increase the P channel mobility by about 3x and that closes the gap to N channel.

In silicon we can apply strain at the edges of the channel and see the benefit. For our very thin quantum well structures we need to grow them on a mismatched lattice to introduce strain. As discussed last time, mismatch can lead to dislocation defects so it is a delicate balance. We will be showing our results at the upcoming IEDM in December but for now here is a graph showing more than 5x mobility improvement over strained silicon by adding ~2% strain to the material.

StrainedIII_V.png

The milestone here is the use of strain to significantly improve hole mobility in III-V P channel and in turn creating a high performance device. Here is a top down view of the III-V quantum well device with a 40nm gate length.

quantumdevice.png

Recapping the challenge list:

  • We have demonstrated we can build N channel quantum well devices on a silicon substrate with equivalent performance to those grown on III-V substrates
  • We can modulate the device operation to act as an enhancement device, not just depletion
  • We can make a fast P channel device to go with the N channel device

Some work in progress:

  • There’s been good research done in the last year on modeling surface preparation and exploring different cleaning techniques in preparation for adding a high-k dielectric (e.g. at Purdue). Achieving high-k will allow us to start calling our devices MOS.
  • These devices are still very big. While there’s been some good work to make short channels and self-alignment (e.g. at MIT), we will likely need a new device architecture to improve the density to compete with silicon

Predicting the past is always easier than predicting the future. It is easier to explain why III-V’s today are not used as broadly as silicon and harder to see where they might be used in the future. Nevertheless I’ll try using our challenge list as a starting point.

If we are able to put III-V devices on the same chip as a sea of silicon devices, then we can add the unique capability that III-V’s bring to existing product designs. For example, RF chips today use III-V’s for high frequency performance and adding this technology to silicon might allow use of multiple radios with better power and performance. Similarly III-V’s are more efficient at emitting light than silicon and adding optical interconnects to a silicon chip would (in principle) become easier. The progress to date is sufficient to start asking what those products would look like and whether they are better than solutions we have today.

If we can make devices that act like conventional CMOS circuits and we can make them on silicon, then we can consider devices which have III-V’s used in blocks for either high performance or in blocks with low operating voltage (0.5V vs 1V for silicon) and mix them with the more dense silicon transistors. Products build on this process should be very useful for handheld devices as the low power blocks would extend battery life in addition to the integrated radio advantage.

If we can make all of the above and also make them dense then III-V technology could replace silicon technology starting around the middle of the next decade. There are many challenges to overcome to achieve this but stay tuned for further progress.

Mike Mayberry is Director of Components Research with Intel’s Technology & Manufacturing Group. Components Research does process technology research.

Comments

Sep 16  |  Joseph said:

Interesting post. I work with quantum dots, but am interested in more direct “devicey” applications.

Any papers you can refer me to regarding engineering mobilities by strain? IIRC, the HH and LH split from strain, but it seems to me that the HH is higher-energy (lower-energy in the hole picture) (regarding the sentence “Strain works by changing the band structure to favor a population of light holes instead of the mixture of heavy and light holes in unstrained material.”)

Sep 16  |  Mike Mayberry said:

Joseph, thanks for the question. Strain is well studied but there are still subtle points being worked out. Some examples 1) strain changes the bending of the bands which directly changes the effective mass at point of the bend, 2) the carriers can repopulate in response and their redistribution across the bands changes the effective mass, and 3) the scattering rate in and out of plane can change as function of the bands which also affects mobility. Our Si strain is uniaxial while the strain discussed here is biaxial and those two have different consequences. I can’t do justice to all of these in a single blog. A good intro paper is “Mobility enhancement” Mohta, N.; Thompson, S.E.; Circuits and Devices Magazine, IEEE Volume 21, Issue 5, Sept.-Oct. 2005 Page(s):18 – 23. A paper that also includes a III-V discussion is “Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance”, Takagi, S.; Iisawa, T.; Tezuka, T.; Numata, T.; Nakaharai, S.; Hirashita, N.; Moriyama, Y.; Usuda, K.; Toyoda, E.; Dissanayake, S.; Shichijo, M.; Nakane, R.; Sugahara, S.; Takenaka, M.; Sugiyama, N.; Electron Devices, IEEE Transactions on Volume 55, Issue 1, Jan. 2008 Page(s):21 – 39

Sep 16  |  Joseph said:

Thanks for the articles and clarification. Is very interesting stuff. More like this, please! :)

Sep 18  |  Scot, KA3DRR said:

Mr. Mayberry,

Can you further explain “RF chips today use III-V’s for high frequency performance and adding this technology to silicon might allow use of multiple radios with better power and performance.”

Specifically, silicon might allow use of multiple radios with better power and performance? As a ham radio operator, I found your statement piqued my curiousity.

Thank you for your time.

Research@Intel · Enforcing Moore’s Law Through Technology Research (guest blog)

Research@Intel · Enforcing Moore’s Law Through Technology Research (guest blog).

Enforcing Moore’s Law Through Technology Research (guest blog)

posted by Sean Koehl on August 20, 2007

As an editor of the Research@Intel blog, I sometimes have the opportunity to share a guest post to complement those coming from our regular bloggers. Today’s post comes from Mike Mayberry of Intel’s Technology & Manufacturing Group. Mike is Director of Components Research, the group at Intel which does process technology research.

In this blog, I’ll relate some of the recent advances in compound semiconductors, but first a little background. There’s an old joke that “Gallium Arsenide is the technology of the future, never the technology of the present” and like all jokes there’s a kernel of truth. Unlike silicon, a compound semiconductor is made up of two elements, gallium and arsenic for example (GaAs). Using two elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. While 300mm diameter silicon wafers are produced in huge quantities, GaAs wafers are typically 150mm, which translates into a huge cost disadvantage. Consequently today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs.

Despite the history, Intel has several active programs looking at compound semiconductors as a possible option for the middle of the next decade. We’re interested in compound semiconductors because of their high charge mobility. Mobility is a measure of how easily you can move charges within the material with application of an electric field. Higher mobility can produce faster devices and/or devices that require much less power. GaAs has about 8x higher mobility compared to silicon, and indium antimonide (InSb) has 50x higher. We’ve previously shown that you could achieve more than 10x improvement in power for an InSb device operating at 0.5V compared to the equivalent silicon device (see our IEDM 2005 presentation). The sticky point is that we have to figure out how to make these in high volumes, which would be impossible if we were limited to small GaAs wafers as starting material.

Most research isn’t based on sudden breakthroughs in thinking but a lot of hard work that builds on other good research. Along the way some things turn out to be easier and others harder, so having a guiding vision can separate great results from the ordinary. For this case we broke down the overall problem — how to make these in high volume — into five individual challenges:

  • Build compound semiconductor devices on silicon substrates. This would allow us to reuse the highly refined silicon infrastructure including 300mm wafers and gives us the option down the road of integrating a few specialized devices with a sea of silicon devices.
  • Find a suitable high-K gate dielectric. Due to the different surface, the silicon high-K solution won’t work as is but we can leverage knowledge we gained to help guide us.
  • Build a high performance PMOS device to go with the existing NMOS. This is needed to have power efficient CMOS logic though some special circuits can get by with just one type.
  • Build enhancement devices. Most existing work is based on depletion mode where you apply a voltage to shut them off. Power efficiency demands that those devices be normally off.
  • Make them small enough to compete with silicon transistor densities. If we stop at integrating only a few specialized devices then this is not needed but then we also won’t reap the full benefit of the technology.

We are working both in our internal labs as well as with such external groups as universities to make progress on this list of challenges.

Starting with item one, the reason people don’t regularly grow compound semiconductors on silicon is due to the mismatch in lattice spacing. That mismatch produces defects that degrade the performance of the devices. Here’s a TEM of GaAs grown on silicon that illustrates the problem. The dark wavy lines are dislocation defects that short-out the device when you try to operate it.

Picture1.jpg

To successfully grow working devices we first grow a buffer layer to absorb most of the mismatch and then we engineer a succession of thinner layers that get closer to the desired lattice spacing. It is a delicate task as the final device is a few 10s of nanometers thick and so currently we use molecular beam epitaxy (MBE) to deposit each atomic layer individually. Here’s a TEM of the quantum well (the region where electrical switching occurs) and you can just make out the individual atomic layers.

Picture2.jpg

As of this summer we have achieved success at fabricating high performance devices using two material types, InSb and InGaAs, and in each case they perform as well as their counterparts on GaAs wafers. Here is the maximum frequency of depletion mode devices plotted against power dissipation. You can see the two InGaAs curves overlap each other and also are significantly better, both higher performing and less power, than equivalently sized silicon devices.

Picture3.gif

This is a major milestone! In the past others have made poorly performing devices on silicon but these are the first reports of high performance devices on silicon. We have published these results recently including the graph above (IEEE Electron Device Letters, Vol. 28, No. 8, August 2007, pp.685-687). At the upcoming IEDM conference in Dec. we will show even newer results for much thinner buffer layers as well as data on enhancement mode devices (#4 on the list).

As usual, we pause briefly to celebrate and then we go back to work on the rest of the list. We’ve made considerable progress in generalizing the growth solutions as we’ve demonstrated by the multiple material types and this will give us flexibility and choices for further research and development. We know Moore’s Law can continue if we invent the right things and it is our job to make sure Intel can continue to deliver advanced technology on time, every time.

Editors Note: Please address comments to Mike — I’ll pass them on to him.

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