Japan’s MIRAI Project seeks to develop a MOS Schottky barrier source transistor with a channel length
Kenji Tsuda, Asia Contributing Editor — Semiconductor International, 1/27/2009
Japan’s Millennium Research for Advanced Information Technology (MIRAI) project announced plans to develop a MOS Schottky barrier source transistor with a channel length &10 nm.
The MIRAI project is studying the ballistic operation of a MOS transistor with a &10 nm channel length. The 10 nm length is considered to be the mean free path (MFP) of electrons in a silicon semiconductor, with no collision of electrons as they move to the drain from the source. In a conventional MOS transistor with a >10 nm channel, electrons collide with the silicon lattice, and are accelerated by the electric drain field (E). The average velocity (v) of electrons is shown as v=μE (μ: electron mobility). The current is expressed with J=qvn (q: electron charge, n: electrons), meaning that a larger current needs a higher velocity and a larger electron density.
In the case of a sub-10 nm channel MOS transistor, electrons from the source can move toward the drain without collision with the lattice. In a ballistic transistor, however, the electrons may arrive at the drain without enough velocity. As a result, drain current may not be large enough, meaning insufficient current drivability. The MIRAI project plans to improve the ballistic operation as one of its research themes within its Ultra-Scaled CMOS Design program.
Toshihiko Kanayama, director of the Nanodevice Innovation Research Center at the National Institute of Advanced Industrial Science and Technology (AIST, Tokyo), leads the Ultra-Scaled CMOS team that plans to develop a new transistor using the source Schottky barrier. The idea is to boost the initial electron velocity at the source edge. In conventional transistors, the initial velocity of electrons at the source edge is almost zero and the electrons are accelerated by the drain voltage, but the Schottky barrier in the new transistor design boosts electron energy at the source edge to increase the initial velocity of electrons.
A target of the research is to increase CMOS drive current by 15%, and to reduce current consumption by 20%. The basic structure consists of high-k/metal gate dielectric film as well as a 3-D tri-gate or finFET structure to strengthen the gate potential. Kanayama’s team has created prototype transistors with a nickel silicide barrier at the source and drain edges. But in the initial stage, the transistor current is not high enough because a mirror effect at the source may lower the barrier, along with a tunneling effect. The project team is working with Hideaki Tsuchiya, an associate professor at Kobe University, to establish a Monte Carlo simulation of the electron behavior from the source to the drain.