Doodles … and mobility enhancement
The Intel “Doodle” advertisement went public recently. While an actress plays me (the idea is the actress is younger, prettier and taller than I am J) the doodles are mine and capture technical highlights of various Intel projects I’ve been involved with. There has been significant curiosity about the Doodle itself and so I’ve given a couple of talks recently to “unpack” the Doodle for interested audiences (a hyperlinked version of these talks is at http://www.intel.com/pressroom/kits/advancedtech/ scroll down to the doodle and click on the pictures for a discussion of each one).
In giving these talks, I am continually reminded of the importance of mobility enhancement in Intel’s long term technical roadmap. (Remember that transistor drive current is directly proportional to mobility, and so any improvement in mobility is a 1 for 1 improvement in drive current and thus performance).
The most significant mobility enhancement technique is transistor strain. Strain was first introduced by Intel in the 90nm generation (http://download.intel.com/pressroom/kits/advancedtech/pdfs/Mark_Bohr_story_on_strained_silicon.pdf ), and its contribution to Intel’s transistor scaling roadmap has increased each generation. Intel has pioneered a number of strain techniques including CESL (strain from the contact etch-stop layer), e-SiGe (strain from including SiGe in the source/drain regions), strain directly from the contact metal, and (with HiK-metal gate) strain enhancement produced by the HiK-MG replacement gate process and strain directly from the metal gate (for key Intel papers see C. Auth at IEDM 2008, http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_VLSI2008_ppt.htm and http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_VLSI2008_doc.htm for a graphical history see K. Kuhn at IWCE 2009, http://download.intel.com/pressroom/pdf/kkuhn/Kuhn_IWCE_invited_slides.pdf starting after pg. 40).
Another option for mobility enhancement is using a different Si substrate orientation (for example, 110 vs 100). This is more complex than it sounds, as NMOS is better on 100 and PMOS is better on 110, and both cannot exist on the same simple (read cheap!) wafer. A critical question with this approach is just how much the PMOS improves and the NMOS degrades – because, if the NMOS degradation is small enough, this is still worth doing (see P. Packan at IEDM 2008, http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_IEDM2008_ppt.htm and http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_IEDM2008_doc.htm ). Now, it IS possible to fabricate the NMOS transistor horizontally and the PMOS transistor vertically to get the optimal orientation in both cases. The issue here is process and design rule complexity (i.e. high cost!). Another alternative (for example, the IBM HOT process) is to integrate both crystal orientations on the same wafer. The issue here is … HIGH COST!
A longer term option is replacement of silicon by new channel materials (for example, Ge or III-V materials). Note that while replacing the entire wafer with Ge or III-V is incompatible with modern 300mm manufacturing, replacing only the channel with Ge or III-V materials is a potentially manufacturable approach.
While Ge is a very well known semiconductor (the first transistors were made of Ge!), the concern with Ge is that its native oxide (GeO) is a poor thermally unstable oxide. A fascinating option is to make Ge transistors with HiK dielectrics rather than GeO – however, this is not a trivial challenge! Even today, there is no known method for fabricating thin (say 1nm EOT) high mobility dielectrics on Ge (literature results reporting exceptional mobilities are from thick gates). Another issue is the narrow bandgap of Ge, which increases band-to-band tunneling and results in higher standby leakage (Ioff). Still another issue is the lattice mismatch between Si and Ge; which can result in various defects and dislocations.
III-V materials are both more challenging and have more potential than Ge. As with Ge, integration of gate dielectrics is a major challenge. As with Ge, the low Eg III-V materials (ex: InAs, InSb, Ge) are subject to standby leakage (Ioff) increases due to band-to-band tunneling (and the effect worsens with strain). The very high mobility materials (ex: InAs, InSb) have low density of states in the gamma-valley, resulting in reduced drive currents. Last, but not least, III-V materials are also lattice mismatched to Si, creating various defects and dislocations. However, in spite of these challenges, Intel has recently reported integration of a composite high-k gate stack on InGaAs (see M. Radosavljevic, IEDM 2009, link pending) as well as the major milestone of improved low power performance of III-V over Si for the voltage range of 0.5-1V (see G. Dewey, IEDM 2009, link pending).
Stay tuned, next month – IEDM, 32nm and what that means for the all new 2010 Intel® Core Processor Family