Transmission Line Pulse (TLP) is an Effective Analysis Tool for ESD | ECN: Electronic Component News
lectrostatic discharge (ESD) occurs when objects – including people, furniture, machines, integrated circuits or electrical cables – become charged and discharged. Electrostatic charging brings objects to surprisingly high potentials of many thousands of volts in ordinary home or office environments. ESD produces currents which can have rise times less than a nanosecond, peak currents of dozens of Amps and durations that can last from tens to hundreds of nanoseconds. Unless ESD robustness is included during design, these current levels can damage electrical components and upset or damage electrical systems from cell phones to computers.
ESD tests ensure that electrical components and systems can survive the ESD stresses that they will encounter. Active components such as integrated circuits and transistors are tested using the Human Body Model (HBM)1 and the Charged Device Model (CDM)2 to ensure they can be handled without damage during manufacture in a controlled ESD environment. Systems are tested for use in non-ESD controlled environments according to IEC 61000-4-23.
A common drawback of ESD tests is the limited information they return. A component or system is stressed at a voltage level, and the unit either survives the stress or it does not. There is no further information. In 1985 T. Maloney and N. Khurana4 introduced Transmission Line Pulse (TLP) as a way to study integrated circuit technologies and circuit behavior in the current and time domain of ESD events. The method became indispensable for integrated circuit ESD protection development, especially after Barth Electronics introduced the first commercial TLP system in the mid-1990s.
|Figure 1. This simplified schematic of a time domain reflection TLP system is an idealized view of the captured waveforms and how they are used to build up a TLP I-V curve. (Click to enlarge)|
Time Domain Reflection TLP
Time Domain Reflection (TDR) TLP with a 100 ns pulse length is the most common version, shown schematically in Figure 1. A 50? transmission line is charged through a high value resistor. The length of the transmission line determines the length of the pulse. Flipping switch S initiates a pulse which travels on 50? cable, through an attenuator, to the device under test (DUT), and reflects from the DUT back to the attenuator. The 50? 10X attenuator prevents multiple reflections. Voltage and current probes between the attenuator and the DUT capture the pulse waveforms on a single shot digital oscilloscope.
The voltage and current at the DUT is the sum of the incident and reflected pulses. For 100 ns TLP systems, the incident and reflected pulses overlap at the voltage and current probes. Therefore, the oscilloscope directly measures DUT voltage and current in the pulse overlap region. The measurement of a voltage current pair is illustrated in Figure 1 for a <50? DUT. The voltage current pair provides a single point on an I-V curve. A full I-V curve for a DUT is mapped out by charging and discharging the transmission line at progressively higher voltages. Commercial 100 ns TLP systems produce current pulses from 1 mA up to 10A or 20A into a short. Most TLP systems can also measure DC leakage after each pulse, allowing the system to detect damage to the sample.
Example of TLP Use
Figure 2 illustrates TLP measurements on a simple circuit element — a grounded gate nMOS transistor. Grounded gate nMOS transistors are often used as protection elements within CMOS ICs. An nMOS specifically designed for ESD can carry considerable current without damage. Without proper design, nMOS transistors are very sensitive to ESD. Figure 2a illustrates TLP stress applied to the drain relative to the grounded source with the gate tied to the source. Figure 2b is a typical TLP I-V curve of an nMOS transistor. At low TLP stress, the transistor is off and no current flows. When the stress voltage reaches the avalanche breakdown of the drain, current begins to flow. At Vt1, It1, sufficient current flows to turn on the parasitic bipolar transistor formed by the drain (collector), substrate (base) and source (emitter). The turning on of the bipolar transistor results in a drop in voltage, often called bipolar snapback. The bipolar region is characterized by Vsb, the snapback voltage, and the resistance of the snapback region, R. The snapback region ends at the second breakdown point, Vt2, It2.
|Figure 2. Sample TLP I-V and leakage evolution on a grounded gate nMOS device. (Click to enlarge)|
The TLP I-V is most useful when combined with the leakage measurements in Figure 2c. After each TLP pulse, the leakage of the nMOS is measured. The leakage is plotted on the X axis, and the pulse current on the Y axis. The Y axis scale for Figures 2b and 2c are the same, allowing easy comparison. Figures 2b and c show that the transition from avalanche to snapback at Vt1, It1 results in no increase in leakage. The second breakdown transition at Vt2, It2 does result in device damage. The parameters in Figure 2b provide a great deal of information about the ESD properties of the nMOS. Vt1 is the voltage needed to trigger the protection properties of the nMOS. Vsb and R can be used to predict voltage drops across the nMOS during an ESD event. It2 is a measure of the transistor’s ability to carry current during an ESD event.
TLP is an indispensable tool for understanding the electrical properties of integrated circuits at the times and current levels of ESD events. In the study of HBM, 100 ns pulses are used and recently, 5 ns and shorter Very Fast TLP (VF-TLP) pulses have explored the CDM time scale. TLP can be used on individual circuit elements, input and output buffers, and full integrated circuits. In addition to measuring I-V curves, TLP can be used to study time dependence and turn on time.
Robert Ashton joined ON Semiconductor in 2007 in the discrete products division as a senior protection and compliance specialist after three years as director of technology at White Mountain Labs, a provider of ESD and latch-up testing of integrated circuits. He has published numerous articles on ESD testing of integrated circuits, test structure use in integrated circuits and CMOS technology development.
1 JEDEC JESD22-A114D Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM.)
2 JEDEC JESD22-C101C Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
3 IEC 61000: Electromagnetic compatibility (EMC) Part 4-2: Testing and measurement techniques Electrostatic discharge immunity test.
4 T Maloney and N Khurana, “Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena,” in Proceedings of the EOS/ESD Symposium 7, (Minneapolis, MN: ESD Association: 1985): 49–54.