Intel’s 32-nm Clarkdale Shows Many Changes

http://www.semiconductor.net/blog/Chipworks_Inside_Angle/23620-Intel_s_32_nm_Clarkdale_Shows_Many_Changes.php
October 6, 2009
Recently we at Chipworks managed to get our hands on some of Intels hot (not to say smoking!) new 32-nm Clarkdale/Westmere microprocessors. Needless to say they went straight into the lab, so that we could get a look at the changes from the 45-nm high-k, metal gate (HKMG) generation.
To be honest, I was expecting more or less a straightforward shrink of the earlier process, possibly with a lower-k intermetal dielectric; however, while its a bit speculative, I dont think we can say that.
However, lets start with some numbers. At IEDM [1] last year, Intel announced a contacted gate pitch and M1 – M3 (1x) metal pitch of 112.5 nm; – we see ~113 nm, so the same, allowing for measurement error. SRAM cell size was given as 0.17 µm2, exactly what we have found. The physical gate length was reduced from 35 nm in the 45-nm process to 30 nm in the new generation; the smallest we have found so far is ~28nm.
(Here we have to remember that the functional gate length is actually set by the sacrificial polysilicon gate used for all the source/drain engineering, but all that we can see is the final metal gate dimension. At the 45-nm node that was ~42 nm, for an announced gate length of 35 nm, giving a ~7-nm difference. It seems likely that there was some sidewall on the poly gate, which was also removed before metal gate formation.)
The smallest metal gate that we have seen is ~35 nm, so making the possibly dubious presumption that the difference is similar, that gives us a functional gate length of ~28 nm.
Fig. 1 shows a comparison of Intels SRAM IEDM image with our de-layered sample at the gate level; a subtle change in the aspect ratio of the cell from 2.6:1 to 2.8:1, but the same cell area.
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Fig. 1 Intel IEDM SRAM (left) and actual product de-layered to gate transistor level

Fig. 2 uses an image from Mark Bohrs talk [1] at the Intel Developer Forum (IDF) a couple of weeks ago, illustrating a 32-nm NMOS transistor, paired with our image of the 45-nm NMOS device (I would love to show our images of the Clarkdale transistors, but that will have to wait until our customers have seen them). The 32-nm image was taken before contact formation; we can see raised epitaxial source/drains and the different conformation of the high-k (the dark layer lining the metal gate) compared with the 45-nm image. In the 45-nm process we were pretty well convinced that the high-k layer went down before the dummy poly gate, now it appears that its formed after the poly gate removal.
Were also wondering what type of strain Intel are using for NMOS at this node – the tensile nitride layer used as the main stressor at the 90- and 65-nm nodes is now practically non-existent. The other strain techniques used at 45-nm (stressed gate fill metal and contact metal) will have less impact at 32; there is less metal fill in the smaller gate, and the raised source/drains will reduce the effect of contact stress. Memorized stress could be present, but it seems unlikely that it could make up the difference.
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Fig. 2 Intel IDF image of 32-nm NMOS gate (left) and Chipworks image of 45-nm NMOS gate

Now the speculation comes in – if we squint hard at the right edge of the 32-nm gate in Fig. 2, its just possible to see what looks like a boundary similar to the e-SiGe in a PMOS transistor. Ive marked it up symmetrically in Fig. 3, with a 45-nm PMOS image for comparison.
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Fig. 3 Comparative cross-sections of Intel 32-nm NMOS (left) and 45-nm PMOS transistors

The use of epi in NMOS raises the possibility of carbon-doped source/drains (e-SiC) to apply tensile stress; research has been going on into this for a while, but the solubility of carbon in silicon is very low, and it is difficult to get into substitutional atomic sites in the crystal lattice. Carbon also has a low atomic number, and in low concentration there will be little atomic number contrast in the TEM image to show up the epi, so its not surprising its barely visible; unlike the e-SiGe in the case of PMOS. We are working on confirming (or denying) this as I write – more news to come! If e-SiC is being used for NMOS strain, it will be yet another first to production for Intel.
Just so that this is not completely speculative, we did a bit of digging around Intels patents, and found US patent 7,402,872, vaguely titled Method for Forming an Integrated Circuit. However, in the description, we have the following (column 6, lines 1 – 14)
Under these conditions, carbon and phosphorus dopants can be substitutionally incorporated into the silicon crystal lattice at concentrations of approximately 1-2 atomic percent and 1-3E20 atoms/cm.sup.3, respectively. The carbon dopant forms an alloy with the silicon, and the phosphorus dopant provides an electrically active species within the alloy. Unlike prior art implant methods, the carbon and phosphorus are substitutionally incorporated into the silicon crystal lattice during the deposition process and the electrically active dopant species (i.e., phosphorus) concentration is essentially equal to the total phosphorus concentration, i.e., 100% activation. In one embodiment, the carbon and phosphorus doped epitaxial silicon film will have a thickness in a range of approximately 1000-3000 Angstroms.
We also found 7,494,858, which describes the wet etch used to form the source/drain cavities aligned on the (111) planes, before deposition of the doped epitaxial source/drains. Also, in this patents description, we have a reference to e-SiC (column 5, lines 32 – 53):
In an NMOS device, source 600 and drain 601 are epitaxially deposited silicon doped with carbon, and may further be in situ doped with phosphorus. The carbon concentration ranges from 0.5 atomic % to 3 atomic % and phosphorus concentration from 5E19 cm-3 to 5E20 cm-3. In an embodiment, the silicon film includes approximately 1.5 atomic % carbon, approximately 1E20 cm-3 phosphorus, and has a thickness of approximately 100 nm. For the NMOS device, such a carbon doped silicon film imparts tensile strain to the channel region, thereby increasing the electron mobility.
These patents were filed back in 2005 and early 06, so Intel has had some time to work out the wrinkles of making e-SiC manufacturable. Other literature such as IBMs paper at IEDM [2] last year indicates that anneal cycles are becoming functional.
The PMOS devices continue to use e-SiGe strain, but pushed even further than in the 45-nm process. This technique is turning out to be a really big handle for cranking up the channel strain, to the point where PMOS drive current has gone from ~30% of NMOS to almost 80% (see Fig.4). At an Intel analyst briefing just before IDF, Mark Bohr confirmed that this trend will continue into the 22-nm generation that was announced at the meeting, so we have the prospect of PMOS drive currents being almost equal to NMOS.
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Fig. 4 Intel NMOS and PMOS drive currents

If we look above the transistors, Intel has been steadily increasing the porosity of the low-k dielectric in the metallization stack; even though theres been no announcement confirming 2nd-generation low-k, it looks similar to the 2nd-gen material we have seen in other chips (Fig.5). We see low-k in the M1 – M7 levels of the nine-metal stack.
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Fig. 5 Metal 3 lines and low-k dielectric

We will be completing our analyses over the next few weeks, and in addition to our usual structural analysis report, well be doing package analysis and transistor characterization reports. Stay tuned!
[1] M. Bohr, Silicon Technology for 32nm and Beyond System-on-Chip (SoC) Products, IDF 2009, San Francisco, Session SPCS009
[2] B. Yang et al., High-performance nMOSFET with in-situ Phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor, IEDM 2008, pp. 51 – 54.

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