Qualcomm’s Nowak: 3-D Faces Cost Issues
Qualcomm Director of Advanced Technology Matt Nowak outlined the cost and technology challenges facing 3-D interconnects in a speech at an IEEE 3-D IC conference. “If this technology adds more than 10% to final costs, it will not be widely used in high-volume wireless technology,” he said.
Phillip Garrou, Contributing Editor — Semiconductor International, 10/6/2009
In a plenary speech at the IEEE 3-D IC conference in San Francisco, Qualcomm Inc. (San Diego) Director of Advanced Technology Matt Nowak said 3-D interconnects face plenty of issues that must be dealt with before the benefits of the approach can be realized.
“While 3-D with TSVs currently has significant industry momentum, more development work is needed to bring this technology to high-volume manufacturing,” Nowak said, adding that TSV (through-silicon via) development and characterization needs to move to leading-edge CMOS, containing strained transistors, ultralow-k dielectrics, and thin die.
Although 300 mm equipment installations are beginning worldwide and test chips are being reported, Nowak noted that a number of issues need to be overcome, including:
• Lack of 300 mm lines in production
• Lack of standard process flows
• Unproven yield/reliability
• Unclear supply chain handoffs
• Lack of consensus on cost targets
The attraction of TSVs is apparent for mobile wireless devices looking for low-cost solutions that improve power efficiency while enhancing performance in terms of bandwidth/milliwatt. Noting that Qualcomm today relies on stacked bare die using wire bond and flip-chip, Nowak said 3-D TSV technology would enable “new architectural solutions that can only be realized with such high-density tier-to-tier connections.”
Many potential 3-D IC users are clamoring for immediate standardization, but Nowak said it may be too early to standardize the technical solutions. Standards eventually will be needed for:
• TSV size, tier thickness, via fill material
• Tier-to-tier pin locations and assignments
• Microbump and passivation materials, properties and geometries
• Reliability test methods
Nowak indicated that foundry TSVs, in which the vias are created in the middle of the process flow, made the most sense and would probably end up being the high-volume manufacturing technology of choice.
Although it is still not resolved where the handoff point will be between the foundry and the outsourced semiconductor assembly and test (OSAT) supplier, Nowak pointed out that handle wafer mounting and dismounting must be done by the same group.
After studying the the cost of ownership models of IMEC, Sematech and EMC-3D, Qualcomm derived its own preliminary economics and determined that the overall cost is dominated by post-fab backside processing. One of the technical conclusions the company reached from its cost modeling is that “thinner is better” — going from 50 µm to 20 µm thick layers could reduce the TSV module portion of the total cost by as much as 25% if the added thin wafer handling costs were not substantial.
Nowak said cost will determine the extent of 3-D IC product adoption. “If this technology adds more than 10% to final costs, it will not be widely used in high-volume wireless technology.”