SOI Reduces Dynamic Power, Wafer Costs Coming Down


Silicon-on-insulator (SOI) technology is seeking to penetrate the high-volume market for mobile Internet devices and smart phones. An ARM paper at last week’s IEEE International SOI Conference compared power consumption levels for bulk and SOI. And wafer supplier Soitec said it anticipates volume wafer prices in the $500 range.
By David Lammers, News Editor — Semiconductor International, October 12, 2009
At last week’s IEEE International SOI Conference in Foster City, Calif., researchers from ARM Ltd. (Cambridge, UK) reported on power savings for a 45 nm silicon-on-insulator (SOI) test chip based on a widely used ARM core. The paper was the result of an ARM collaboration with Soitec (Grenoble, France).
The comparison, however, was between a simulation of a bulk 45 nm CMOS low-power (LP) implementation, and physical extractions from a 45 nm SOI test chip. The ARM team said the comparison resulted in a ~40% power savings for the SOI test chip running at 500 MHz, the frequency level that may be required for upcoming smart phones and mobile Internet systems.

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Static power consumption increases modestly when chip temperature increases during operation.

For the past decade, SOI technology has been seeking to break into the high-volume mobile IC space, based on the lower capacitances possible with the buried oxide substrates. Although servers and other high-performance systems have been able to bear the cost of SOI wafers, companies making price-sensitive mobile systems thus far have avoided SOI technology on cost grounds, for the most part.
“Our cost structure is already achieving the target we believe is the right one to penetrate the mobile market,” said Jocelyne Wasselin, director of marketing and business development at Soitec. Customers can anticipate seeing volume wafer prices in the $500 range, she said, down sharply from two years ago when Soitec was quoting ~$800 price levels.
At the SOI conference, the ARM test chip was based on the widely used ARM 1176 core and IBM’s 45 nm SOI process. It was compared with an unidentified bulk 45 nm CMOS technology. The SOI results were based on extractions from silicon, but the ARM team said it was “awaiting the bulk CMOS parts from the foundry.” Due to lack of bulk silicon results, the ARM team said “45 LP simulation results are used to compare with the 45 SOI silicon. At the 500 MHz target frequency, 45 SOI enables a 38% total power reduction compared with 45 LP, despite the high leakage difference, thanks to much lower dynamic power and Vdd scaling.”

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SOI power consumption, measured at three different operating voltages, remains under control at relatively high frequencies. (Source: ARM)

Moreover, the 45 nm LP implementation resulted in a core area of 1.38 mm2, including both logic and memory, while the 45 nm SOI test chip resulted in a 1.28 mm2 core, a 7.3% area reduction.
Although the SOI test chip had lower active power, the static (leakage) power was much higher. Static power was 0.17 mW for the bulk CMOS simulation, and 9.3 mW for the SOI test chip. “The leakage difference is aligned with what we expected from a low power versus high performance technology comparison. It is worth noting that the leakage difference is strongly reduced between 45 LP and 45 SOI when increasing the temperature from 25ºC to 125ºC (from 57× down to 6×),” the Grenoble-based ARM team reported.
If the 45 SOI core frequency is increased to 600 MHz, the total power consumption reaches 75 mW, still 28% below 45 LP running at 500 MHz. The 45 SOI enables a 20% speed improvement over 45 LP along with a 28% power reduction,” the ARM team said.
Horacio Mendez, executive director of the SOI Industry Consortium (Boston), argued that bulk low-power CMOS technology “cannot reach the performance targets for the next-generation mobile Internet devices (MIDs) and smart phones.” Though the general, or G, process offerings “can reach the performance levels for these markets, it is at a significantly higher power consumption, a >50% power increase.”
Mendez said in order for the foundry bulk G processes to reach the performance levels required for MIDs and smart phones, “the technology needs to add considerable complexity — principally deep N well/P well implants and shallow trench isolation complexity — which leads to increased cost. Bulk technology cost is increasing faster than for SOI.”
Mendez said that when the smaller die size is factored in, the total cost difference between SOI and bulk will be in the single digits for the 32/28 nm generation, and will “begin to reach parity at 22 nm.”
IEDM has fully depleted slant
For leading-edge technology developers, fully depleted SOI technology is an active area of interest. At the 2009 International Electron Devices Meeting (IEDM), beginning Dec. 7 in Baltimore, an IBM team will report results from devices fabricated on extremely thin SOI (ETSOI) CMOS, with silicon carbon (SiC) stress techniques. The IBM team claims record low variability for low-power system-on-a-chip applications.
Also at IEDM, a Leti-Soitec-STMicroelectronics team will report on a hybrid fully depleted SOI/bulk high-k/metal gate platform for LP multimedia applications. The Grenoble-based team will report ring oscillator delay improvements of ~15% compared with bulk 45 nm devices.
An IEDM paper given by researchers from the Indian Institute of Technology-Bombay and Infineon Technologies will compare simulated results from planar and non-planar SOI devices. “Non-planar devices perform poorly in comparison to ultrathin body (UTB) planar SOI MOSFETs, and are not the ideal choice for SoC applications,” the paper’s abstract concludes.

  1. volume wafer prices in the $500 range
    SOI test chip had lower active power, the static (leakage) power was much higher
    general, or G, process offerings “can reach the performance levels for these markets, it is at a significantly higher power consumption, a >50% power increase

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