papers for 22nm technology projection

Qualcomm, ASU, 2009 CICC

Xia Li; Wei Zhao; Yu Cao; Zhi Zhu; Jooyoung Song; Bang, D.; Chi-Chao Wang; Kang, S.H.; Wang, J.; Nowak, M.; Yu, N., “Pathfinding for 22nm CMOS designs using Predictive Technology Models,” Custom Integrated Circuits Conference, 2009. CICC ’09. IEEE , vol., no., pp.227-230, 13-16 Sept. 2009

Abstract: Traditional IC scaling is becoming increasingly difficult at the 22 nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess the performance impact of future key modules. In this paper we propose a strategy that enables simultaneous investigation of advanced process and design concepts. Based on a customized predictive methodology and silicon data at 90-45 nm nodes, compact transistor and interconnect models are developed for the next generation CMOS technology. We capture the heuristic device behavior during the scaling, which helps us to gain key insights that allow us to make tradeoffs of circuit performance metrics for next technology node.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5280845&isnumber=5280726

Infineon, 2005 ESSCIRC

Risch, L., “Pushing CMOS beyond the roadmap,” Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European , vol., no., pp. 63-68, 12-16 Sept. 2005

Abstract: Today, the 90nm generation is in production and in spite of many roadblocks, the latest ITRS 04 expects that CMOS can be scaled down to the 22nm node and beyond. However, for conventional bulk CMOS serious challenges are evident and new transistors with better electrostatic channel control, lower off-currents and higher on-currents will be needed. Among them, multi-gate devices with very thin silicon channels are most promising. Several architectures like FinFET, wafer bonded double gate and SON gate all around have been demonstrated with good electrical characteristics at gate lengths of 25-10nm. Under certain assumptions for the SD regions, quantum mechanical simulations predict that silicon MOSFETs can be functional down to 2nm gate length. Multi-gate transistors have also been implemented in high density flash memory cells down to 20nm. Large Vt shifts suitable for multi-level storage were achieved. Therefore, it seems very realistic that the device roadmap will not end at the 22nm node. Assuming that manufacturing and cost issues can be fulfilled, CMOS will continue to dominate in the nanoelectronics era.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1541558&isnumber=32889

Smayling, Michael C.; Axelrad, Valery, “Simulation-Based Lithography Optimization for Logic Circuits at 22nm and Below,” Simulation of Semiconductor Processes and Devices, 2009. SISPAD ’09. International Conference on , vol., no., pp.1-4, 9-11 Sept. 2009

Abstract:

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5290238&isnumber=5290184

Intel, 2009 DAC

Borkar, S., “Design perspectives on 22nm CMOS and beyond,” Design Automation Conference, 2009. DAC ’09. 46th ACM/IEEE , vol., no., pp.93-94, 26-31 July 2009

Abstract: This paper presents technology and economic challenges posed by 22 nm CMOS and beyond, and how they can be addressed by advances in design technology, validation, and testing, to exploit the benefits of scaling we have enjoyed over the decades.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5227192&isnumber=5227020

Purdue, 2009 DAC

Roy, K.; Kulkarni, J.P.; Gupta, S.K., “Device/circuit interactions at 22nm technology node,” Design Automation Conference, 2009. DAC ’09. 46th ACM/IEEE , vol., no., pp.97-102, 26-31 July 2009

Abstract: As transition is being made into 22 nm node, technology considerations and device architectures suitable for such scaled technologies are being explored. To design circuits and systems at scaled nodes, we believe there is a need for technology aware circuit and system design methodology that considers device architecture, and technology challenges to achieve design optimality. In this paper, we discuss the challenges of device-circuit-system design at the 22 nm node and present techniques at different levels of design abstraction to meet these challenges. In particular, we discuss different device options for multi-gate FETs. Logic and memory design using multi-gate FETs is also considered. Finally, we briefly discuss process variation tolerant system design methodologies for such scaled technologies.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5227190&isnumber=5227020

PDF solution, 2009 DAC

Strowjas, A.J.; Jhaveri, T.; Rovner, V.; Pileggi, L., “Creating an affordable 22nm node using design-lithography co-optimization,” Design Automation Conference, 2009. DAC ’09. 46th ACM/IEEE , vol., no., pp.95-96, 26-31 July 2009

Abstract: Achieving the required time-to-market with economically acceptable yield levels and maintaining them in volume production has become a daunting task for the advanced technology nodes. These difficulties are primarily attributable to the increase in process variability that is incurred while aggressively scaling technology nodes which are based on the same fundamental device architectures and process solutions. The introduction of a metal gate/high-K (MGHK) stack at the 32/28 nm technology node will help in addressing the random variations due to random dopant fluctuations (RDF), but its benefit will be exhausted after a single process generation. As a result, for the 22/20 nm technology nodes, the only hope to limit RDF will be to adopt novel device architecture, such as FinFET and ultra thin body or fully depleted SOI, that would reduce the dopant concentration in the channel. Moreover, the inability to scale the wavelength of the light source used for lithography has led to a rapid increase of process and design costs. In particular, the lack of progress in extreme ultraviolet lithography (EUVL) will result in the need to define 22 nm technology node using expensive double patterning technologies (DPT) for critical layers. As a result, complex DFM flows have been proposed as an attempt to model various printability and layout dependent effects; however, the increase in design flow complexities, lack of accuracy, and the tremendous expense of maintaining updated models required for these methods has marred their adoption.We will show how template-based design methodology can enable future technology nodes that can utilize current generation lithography while minimizing the cost per good die. In particular, we will: discuss the choices of regular design fabrics and their implications on design metrics, such as power, area, and performance, resulting yields, and overall cost; show that the selection of circuit topologies can be mapped efficiently to the choice of reg- ular design fabric; and compare lithography solutions such as DPT, direct write multi-e-beam (MEBM), and interference lithography (IL) for the 22 nm technology node and beyond.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5227193&isnumber=5227020

IBM 2009 DAC

Anderson, C.J., “Beyond innovation: Dealing with the risks and complexity of processor design in 22nm,” Design Automation Conference, 2009. DAC ’09. 46th ACM/IEEE , vol., no., pp.103-103, 26-31 July 2009

Abstract: This talk will describe the challenges of high-performance microprocessor designs in 22 nm and beyond. The focus of the talk will be on addressing the risks and complexity of this very demanding design domain and what lies beyond the innovation that has been the driving engine of technology so far.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5227191&isnumber=5227020

Toshiba, 2009 VLSI

Goto, M.; Kawanaka, S.; Inumiya, S.; Kusunoki, N.; Saitoh, M.; Tatsumura, K.; Kinoshita, A.; Inaba, S.; Toyoshima, Y., “The study of mobility-tin, trade-off in deeply scaled high-k / metal gate devices and scaling design guideline for 22nm-node generation,” VLSI Technology, 2009 Symposium on , vol., no., pp.214-215, 16-18 June 2009

Abstract: The trade-off between Tinv scaling and carrier mobility (mu) degradation in deeply scaled HK/MG nMOSFETs has been investigated based on experimental results. Ion, components are analyzed in terms of NS, vinj and SCE in Lg= 25 nm devices for the first time. As a result, it is clarified that the aggressive Tinv scaling can achieve the performance improvement even if mu degradation occurs in some degree, because mu impact decreases with Lg and Tinv scaling impact becomes strong. Furthermore, we have introduced the effective Tinv scaling (novel SiON) process and demonstrated its excellent device performance (Ion 1 mA/mum @Ioff=100 nA/mum, Lg 25 nm, Vdd=LOV, Avt=1.8 mV mum, Tinv 1.13 nm, without any performance booster technology).

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5200604&isnumber=5200578

Global Foundry, 2009 VLSI

Choi, K.; Jagannathan, H.; Choi, C.; Edge, L.; Ando, T.; Frank, M.; Jamison, P.; Wang, M.; Cartier, E.; Zafar, S.; Bruley, J.; Kerber, A.; Linder, B.; Callegari, A.; Yang, Q.; Brown, S.; Stathis, J.; Iacoponi, J.; Paruchuri, V.; Narayanan, V., “Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond,” VLSI Technology, 2009 Symposium on , vol., no., pp.138-139, 16-18 June 2009

Abstract: We report for the first time that extreme EOT scaling and low n/p VTHs can be achieved simultaneously. Underlying mechanisms that enable EOT scaling and EWF tuning are explained and the fundamental device parameters including reliability of the extremely scaled devices are discussed. Record low gate leakage, appropriately low VTHs and competitive carrier mobilities in this work demonstrate the gate stack technology that is consistent with the sub-22 nm node requirements.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5200663&isnumber=5200578

IIT, 2009

Hentrich, D.; Oruklu, E.; Saniie, J., “Performance evaluation of SRAM cells in 22nm predictive CMOS technology,” Electro/Information Technology, 2009. eit ’09. IEEE International Conference on , vol., no., pp.470-475, 7-9 June 2009

Abstract: Static Random Access Memory (SRAM) units are often directly integrated onto the same die with the microprocessors and influence the design metrics significantly. SRAM often consumes large percentages of the die size and their leakages significantly contribute to the static power dissipation of those chips. The main objective of this article is to characterize the speed and power consumption of five different SRAM cells in a predictive high performance 22 nm transistor process and in a predictive low power 22 nm transistor process. The five types of studied cells are traditional 6T, gated-ground 7T, full Self- Controlled Voltage Level (SVL) 12T, SVL 9T Footed, and SVL 9T Headed. The simulation results indicate that the timing behavior of SRAM cells are largely the same but power dissipation, leakage power in particular, vary significantly in 22 nm technology. The gated-ground 7T cells are deemed superior in the high performance process, while traditional 6T cells are deemed the best in the low power process.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5189662&isnumber=5189546

Hirosh Iwai, 2009

Iwai, H., “Technology roadmap for 22nm and beyond,” Electron Devices and Semiconductor Technology, 2009. IEDST ’09. 2nd International Workshop on , vol., no., pp.1-4, 1-2 June 2009

Abstract: Logic CMOS technology roadmap for dasia22 nm and beyondpsila is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Regarding the downsize limit, it would take probably 20 to 30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5166100&isnumber=5166089

IMEC, 2009 VLSI

Zahid, M.B.; Pantisano, L.; Degraeve, R.; Aoulaiche, M.; Trojman, L.; Ferain, I.; San Andres, E.; Groeseneken, G.; Zhang, J.F.; Heyns, M.; Jurczak, M.; De Gendt, S., “Advanced electrical characterization toward (sub) 1nm EOT HfSiON – hole trapping in PFET and L-dependent effects,” VLSI Technology, 2007 IEEE Symposium on , vol., no., pp.32-33, 12-14 June 2007

Abstract: Hf-based gate dielectrics layers with EOT1nm are actively investigated for 22nm node and beyond. EOT scalability of these films is simultaneously achieved by reducing the high-k thickness as well as optimizing the N-profile into the thin film. For Hf-based layers electron traps in the upper part of the bandgap have been a major concern for nMOSFETs since they cause VT-instability and affect mobility [1]. With the scaling of EOT to 1 nm and below, the impact of these traps has, however, disappeared [2]. Electron traps have never been considered a potential problem for PMOS because at negative bias they are always efficiently discharged. We found, however, that in PMOS with EOT ˜1 nm, a large hysteresis at high field is observed in the ID-VG characteristics, while no hysteresis is measured on the corresponding NMOS devices (on the same wafer) (Fig. 1). In this work we will prove by an advanced charge pumping technique that the hysteresis in PMOS is caused by hole traps in the high-k layer. Furthermore, we show how NBTI defects are correlated with such hole traps. Hole trap density depends on the Hf- and N-profile in the film, being larger for Hf-rich films.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4339715&isnumber=4339665

Sematech, 2008 IEDM

Huang, J.; Kirsch, P.D.; Heh, D.; Kang, C.Y.; Bersuker, G.; Hussain, M.; Majhi, P.; Sivasubramani, P.; Gilmer, D.C.; Goel, N.; Quevedo-Lopez, M.A.; Young, C.; Park, C.S.; Park, C.; Hung, P.Y.; Price, J.; Harris, H.R.; Lee, B.H.; Tseng, H.-H.; Jammy, R., “Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application,” Electron Devices Meeting, 2008. IEDM 2008. IEEE International , vol., no., pp.1-4, 15-17 Dec. 2008

Abstract: For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls Vt, as well as strongly affects mobility, Nit and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved Vt tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO2) IL. Tinv=1.15 nm and Vt,lin=0.31 V was obtained while achieving the following attributes: mobility~70%, Nit <5times1010 cm-2, DeltaVt<30 m V within wafer, BTI DeltaVt <40 m V at 125degC. By optimizing these gate stack factors, we have developed and demonstrated structures for 22 nm node LOP application.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4796609&isnumber=4796592

UCB, 2006 VLSI TSA

Lin, C.H.; Das, K.K.; Chang, L.; Williams, R.Q.; Haensch, W.E.; Hu, C., “VDD Scaling for FinFET Logic and Memory Circuits: the Impact of Process Variations and SRAM Stability,” VLSI Technology, Systems, and Applications, 2006 International Symposium on , vol., no., pp.1-2, 24-26 April 2006

Abstract: As CMOS technology is fast moving towards the scaling limit, the FinFET is considered as the most promising structure down to 22nm node (Frank et al., 1992; Huang et al., 1999). Both FinFET-based logic and SRAM have been demonstrated recently (Rainey et al., 2002; Nowak et al.,2002). However, with scaling of the device dimensions, process-induced variations cause an increasing spread in the distribution of circuit delay and power, and affecting the robustness of VLSI designs (Burnett et al., 1994). SRAM has become the focus of technology scaling since embedded SRAM is estimated to occupy nearly 90% of the chip area in the near future (2003). Due to the area-constrained limit, the device fluctuation in the SRAM cell is significant. In this paper, we explore the performance of FinFET technology in digital circuit applications at 90 nm technology node under various device parameter variations. Comprehensive comparison of FinFET vis-a-vis PD-SOI has been done for logic gates as well as memory structures that are most commonly used in commercial VLSI designs. We also compare the performance of these two technologies at ultra-low voltages for future low-power applications

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4016592&isnumber=4016579

U of Florida, Sematech, 2008 VLSI

Suthram, S.; Sun, Y.; Majhi, P.; Ok, I.; Kim, H.; Harris, H.R.; Goel, N.; Parthasarathy, S.; Koehler, A.; Acosta, T.; Nishida, T.; Tseng, H-H.; Tsai, W.; Lee, J.; Jammy, R.; Thompson, S.E., “Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node,” VLSI Technology, 2008 Symposium on , vol., no., pp.182-183, 17-19 June 2008

Abstract: For the first time strain additivity on III-V using prototypical (100) GaAs n- and p-MOSFETs is studied via wafer bending experiments and piezoresistance coefficients are extracted and compared with those for Si and Ge MOSFETs. Further understanding of these results is obtained by using multi-valley conduction band model for n-MOS and performing k.p simulations for p-MOS. For GaAs n-MOSFET, uniaxial tensile stress is shown to enhance performance only for small stresses biaxial tensile stress is shown to be more beneficial. Importantly uniaxial compressive stress is beneficial for GaAs pMOSFETs and the piezoresistance effect is much larger than that seen for Si MOSFETs along the <110> channel direction. This works shows that intrinsic mobility and stress induced mobility enhancement are key knobs for scaling of III-V CMOSFETs.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4588611&isnumber=4588540

IBM, 2008 VLSI

Guillorn, M.; Chang, J.; Bryant, A.; Fuller, N.; Dokumaci, O.; Wang, X.; Newbury, J.; Babich, K.; Ott, J.; Haran, B.; Yu, R.; Lavoie, C.; Klaus, D.; Zhang, Y.; Sikorski, E.; Graham, W.; To, B.; Lofaro, M.; Tornello, J.; Koli, D.; Yang, B.; Pyzyna, A.; Neumeyer, D.; Khater, M.; Yagishita, A.; Kawasaki, H.; Haensch, W., “FinFET performance advantage at 22nm: An AC perspective,” VLSI Technology, 2008 Symposium on , vol., no., pp.12-13, 17-19 June 2008

Abstract: At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4588544&isnumber=4588540

Sematech, 2009 VLSI-TSA

Huang, J.; Kirsch, P.D.; Hussain, M.; Heh, D.; Sivasubramani, P.; Young, C.; Gilmer, D.C.; Park, C.S.; Tan, Y.N.; Park, C.; Harris, H.R.; Majhi, P.; Bersuker, G.; Lee, B.H.; Tseng, H.-H.; Jammy, R., “Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs,” VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on , vol., no., pp.152-153, 21-23 April 2008

Abstract: We demonstrate for the first time a gate first high-k/metal gate (MG) nFET with EOT = 0.74 nm (Tinv = 1.15 nm), low Vt = 0.30 V, high performance [Ion/IOff
= 1310(muA/um) at 100(nA/um)], low leakage (> 200x reduction vs. SiO2/PolySi) and good PBTI. Low-k interface layer scaling and high-k La-doping enable this desirable EOT and Vt. SiON/HfLaSiON can give similar interface quality as SiO2/HfSiON. Device performance was further improved 5% by strain engineering.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4530842&isnumber=4530767

Toshiba, 2008

Ohuchi, K.; Lavoie, C.; Murray, C.E.; D’Emic, C.P.; Lauer, I.; Chu, J.O.; Bin Yang; Besser, P.; Gignac, L.M.; Bruley, J.; Singco, G.U.; Pagette, F.; Topol, A.W.; Rooks, M.J.; Bucchignano, J.J.; Narayanan, V.; Khare, M.; Takayanagi, M.; Ishimaru, K.; Dae-Gyu Park; Shahidi, G.; Solomon, P.M., “Extendibility of NiPt silicide to the 22-nm node CMOS technology,” Junction Technology, 2008. IWJT ’08. Extended Abstracts – 2008 8th International workshop on , vol., no., pp.150-153, 15-16 May 2008

Abstract: This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach 1times10-8 Omega-cm2 for both n+ and p+ Si by using novel test structures of small silicided contact with varied areas from 20-nm diameter to 260-nm diameter by e-beam lithography fabricated on highly doped substrate made by conventional source drain implantation. It demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4540037&isnumber=4539996

Cadence, 2005

Vucurevich, T., “Design Automation in the “Late-CMOS” Age,” ASIC, 2005. ASICON 2005. 6th International Conference On , vol.1, no., pp. XI-XI, 24-27 Oct. 2005

Abstract: Within the next 15 years, we will reach the end of Silicon based CMOS design. This talk will outline some of the challenges and opportunities presented as technology scales from 65nm today down to 22nm in this timeframe. New EDA technology requirements in the areas of Modeling, Synthesis, Functional Verification, and Reliability will be reviewed and some solutions proposed.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1611227&isnumber=33846

UCB, 2008

Jemin Park; Chenming Hu, “Air spacer MOSFET technology for 20nm node and beyond,” Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on , vol., no., pp.53-56, 20-23 Oct. 2008

Abstract: Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20 nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10 nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4734461&isnumber=4734459

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