## Hirosh Iwai’s technology projection beyond 22nm using 2008 ITRS report

Hirosh Iwai, 2009

Iwai, H., "Technology roadmap for 22nm and beyond," *Electron Devices and Semiconductor Technology, 2009. IEDST ‘09. 2nd International Workshop on* , vol., no., pp.1-4, 1-2 June 2009

Abstract: Logic CMOS technology roadmap for dasia22 nm and beyondpsila is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Regarding the downsize limit, it would take probably 20 to 30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5166100&isnumber=5166089

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2007 ITRS |
2008 ITRS |

Print Lg |
X0.71 / 3years | X0.71 / 3years |

Physical Lg |
X0.71 / 3years | X0.71 / 3.8years |

Physical channel length scaling will slow down. At 2020, Lphy is still 9~10nm. Likely patterned by nano-imprint technology.

Along with slowing Lphy scaling, EOT and Xj scaling will be slowed down as well.

Technology trend projected before 2008 update. FinFET and high mobility channel were expected to be in 22nm, but none of them is planned in 22nm.

Also, the pace of the introduction of new

technologies becomes slower. For example, introduction of DG

or fin-gate structure will delay with 4 years, and 22 nm logic

CMOS – which is expected to start production in 2011~12 –,

can be made with the planer bulk CMOS , of course, as shown in

Fig. 2 [2,3].

Planar bulk technology extends to Y2016, 15nm node manufacturing.

DG transistor will be introduced below 15nm, evolving into nanowire structure eventually.

Overall chip clock frequency will slow down as multicore scheme is introduced.

Local chip clock frequency however will keep increasing. 8%/year in 2008 ITRS. 6.3GHz in 2011.

22nm will not be on 450mm wafer. BEOL low k development will keep retarded than ITRS projection.

Vdd scaling is difficult due to Vt scaling is difficult.

Vdd will kept at 0.9V up to Y2020 because of Vt scaling difficulties.

EOT scaling below 5A can be enabled by using La2O3 type High-k, demonstrated as 3.7A already.

Enhanced short channel control will allow Vt scaling, thus Vdd scaling.

8T SRAM cell using separate read and write port is popular to improve cell stability, even though cell area penalty.

This high cell stability will allow low Vccmin, thus lower cell voltage.

Si nanowire will be in 2020 to 2030 solution. Even with alternative channel material, structure will be nanowire shape.

Nano-imprint technology can be used for Si nanowire fabrication (top down).

One dimensional ballistic conduction allows high quantum conduction with 77.8uS per wire regardless of wire diameter and the channel length.

Channel current is multiplied with the number for the quantum channel available for the conduction. Too many quantum channel however degrades ballistic conduction due to carrier scattering between the conduction bands.

There is a trade off between one dimensional ballistic conduction and the number of quantum channel in terms of nanowire width. Small width is good for ballistic transport, but wider width is good for more quantum channel.

After Si nanowire, Ge or 3-5 nanowire can be used, After that, CNT or graphene ribbon FET can be used.

Bio inspired system will be ultimate solution after 2050.

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