Intel Chip Vision: Run Slow to Stay Cool

Intel Chip Vision: Run Slow to Stay Cool
Keeping power under control at data centers is causing a radical reassessment of chip design, according to Shekhar Borkar, Intel’s director of MPU research. Cramming many cores on a die, most of them running at very low frequencies at operating voltages of less than half a volt, is likely to happen over the next decade. And self-aware systems will poll the processors about chip aging issues, such as NBTI.
By David Lammers, News Editor — Semiconductor International, November 18, 2009
To keep power within reasonable limits, Intel Corp.’s director of MPU research, Shekhar Borkar, has a vision of microprocessors with many hundreds of small cores running at slow frequencies, using extremely low operating voltages that hug the threshold voltage. Microprocessors and other chips will be monitored to determine if performance is being affected by aging issues, such as voltage droops or negative bias temperature instability (NBTI).

Shekhar Borkar, Intel fellow

In a keynote speech at the 2009 International Test Conference (ITC), held in Austin, Texas, Borkar said today’s designers might have on the order of 10 billion transistors to play with. At the 6-7 nm node a decade hence, the transistor count may skyrocket to a trillion or so. While the gain in logic transistors over that time period will be ~3×, the memory transistors will increase by ~10×. By then, the overriding concern will be power consumption.
Already, Intel, Microsoft and others are fretting about the amount of power required to run data centers. Looking a decade out, radical changes in technology will be required in order to cram a trillion transistors within a similar power envelope for a >100 Gflop operation. “We can’t have a nuclear power plant sitting next to each data center,” Borkar said. “So how do we do it?”

Radical changes in how chips are designed will be required to keep power consumption within today’s limits. (Source: Intel)

Intel’s vision is to have not just dozens of cores, but many hundreds of cores on each processor. Some critical cores will run at the full frequency, but beyond those few, many cores will operate at relatively slow speeds. Graphics cores, for example, may operate at far slower frequencies than they do today, using parallel operations to compensate.
“We will need very fine-grained power management,” he said. “The network on chip, or NOC, is being studied. But why use a packet-switched mesh if that consumes too much power? It might be more efficient in terms of power to run busses on the die, perhaps 4096 bits wide, and use several cache lines to transmit at lower energy. A hierarchy of busses may be required, working with a packet-switch network.”
Unless EUV lithography achieves a breakthrough, the industry will be stuck with 193 nm immersion lithography, with all the line-edge roughness (LER) challenges that inhibit resolution. Using 193 nm lithography for very advanced technology nodes implies “ever-increasing complexity of the design rules,” Borkar said. “That concerns me.”
Microprocessors today are built using hard-wired, custom-designed macros. But that design style may be replaced by soft macros that can be re-used from one technology node to the next. He cited a recent Toshiba study that used synthesizable cores to achieve a 30% smaller die size than the fully customizable design effort. “What is the future of custom design if there is no die size or performance benefit?” he asked.
Borkar said tomorrow’s microprocessors may operate much as today’s watch chips, with very low operating voltages that are barely above the threshold voltage. Although today’s MPUs have a Vdd of ~1 V and a Vt of perhaps 0.3 V, processors a decade in the future might have many transistors operating at 0.4 Vdd, barely a tenth of a volt higher than the Vt. Although he acknowledged that those cores would be very slow, the issue will be forced by the need to keep power consumption under control.

Running cores at very low frequencies, with the operating voltage near the threshold voltage, may be required.

“We need to be bold and reduce the Vdd. If the frequency declines, that’s OK,” he said. “It will be all about energy, and this voltage tuning can be seen as an act of desperation [to save
power]. We can get performance back by taking advantage of parallelism.”
Intel and other companies are working on in-system monitoring, in which a server will ask the MPU every 10 seconds or so for information that might indicate chip aging problems, such as voltage droop, NBTI and other issues that increase over time. These self-aware, self-diagnosing systems are the focus of intense research efforts, sponsored in part by the Defense Advanced Research Projects Agency (DARPA).

  1. No trackbacks yet.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s

%d bloggers like this: