Intel 32nm Briefing (sep 2009)

Intel 32nm Briefing

Last week I had another chance to hear Mark Bohr present highlights of Intel’s latest process technology. If it wasn’t enough to hear about process development directly from an Intel Senior Fellow who has been there through the transition from metal to poly gates and back again, this time I was lucky enough to also have Sanjay Natarajan on hand to add a few details and answer my questions. Of course, Sanjay is the 32nm Program Manager at Intel who is still keeping his node rolling ahead of schedule.
The latest Intel briefing provided some advance news before the 2009 Intel Developer Forum (IDF) which goes next week in San Francisco. I expect Intel will announce the launch or at least the launch date for the first chips from the Westmere 32nm family of processors at the next IDF event.
Intel’s PR team had two more reasons for holding analyst calls last week. One was to announce two papers that will be presented at IEDM in December. The second, but more significant, is that 32nm product wafers are moving through the D1D fab in Oregon now. I have not quite deciphered the code for what is happening here, but these wafers are “in support of planned Q4 revenue production.” If you take that at face value, then Intel should be shipping 32nm processors to customers before the end of the year. However, none of the people I talked to at Intel were willing to commit to that despite widespread assumptions that they will. That’s why I think important announcements will be made next week because there is no reason to believe product shipments would be delayed at this point.
One of the IEDM papers describes the 32nm process which is Intel’s second generation of high-k metal gate (HKMG) technology. Paul Packan will present 32nm Technology for High Performance CPUs. Dr. Natarajan promises that this Intel presentation will provide more details of the process than past conference papers have. For now, we know that Intel has improved NMOS drive current by 19 percent and PMOS by a whopping 28 percent compared to 45nm. As Mark Bohr pointed out, designers have desired balanced NMOS and PMOS performance since the first CMOS process Intel rolled out in 1981. Perhaps, as he said, we are getting closer to that dream.
Intel process engineers boosted 32nm PMOS transistors saturation currents closer to NMOS by virtue of the fact as Sanjay put it, “There are more knobs to turn in the PMOS process flow.” Since embedded SiGe source/drains strain the PMOS channels to enhance hole mobility in addition to the use of stress liners deposited after the gates, the PMOS devices employ additional strain enhancement techniques compared to the NMOS transistors. Mark Bohr reminded me that the replacement gate flow used by Intel also benefits PMOS transistor performance.
The jumps in drive current – especially the PMOS – are a big achievement, but Intel wants to get the word out about the leakage performance of their 32nm transistors. Record-breaking saturation current is nothing new for Intel, but they can now add the best reported leakage to their press kit. The design flexibility of trading off leakage for drive current has been part of Intel presentations for a while now. The range of transistor performance to match the application has been growing as the technology nodes have been shrinking. Intel also reminds as that there yield ramps are getting faster at each node.
Perhaps the biggest news for Intel’s 32nm process is the introduction of immersion lithography. The new tools are used on critical layers up to metal three to provide Intel with another best – the smallest contacted gate pitch of 112.5nm. Even 28nm processes in the literature cannot best that dimension.
The second IEDM paper announced in the analyst briefing is about the 32nm SoC process. The transistor performance range offered in the new process offers many advantages for non-CPU applications. That could well be the real story of the Intel 32nm process but one I will save that for another post.

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