Nvidia’s Chen Calls for Zero Via Defects – 2009-12-07 23:51:09 | Semiconductor International
Nvidia’s Chen Calls for Zero Via Defects
Nvidia needs zero defects from its foundry partners, particularly in the vias on its leading-edge graphics processors, said John Chen, vice president of technology and foundry operations at the GPU powerhouse. With 3.2 billion transistors on its 40 nm graphics processor now coming on the market, the 7.2 billion vias have become a source of problems that the industry must learn to deal with, Chen said in a keynote speech at IEDM.
David Lammers, News Editor — Semiconductor International, 12/7/2009
As its graphics processors have scaled to billions of transistors per die, leakage power has “become almost intolerable” and the needs for zero defects and zero variability have become paramount, said John Chen, vice president of technology and foundry operations at graphics processor vendor Nvidia Corp. (Santa Clara, Calif.)
In a keynote speech at the International Electron Devices Meeting (IEDM) going on in Baltimore this week, Chen said Nvidia’s 40 nm graphics processor has 3.2 billion transistors, up from ~1 million transistors in 1993 when the company was founded. Although the increasing transistor count has allowed near photo-realistic moving graphics, Chen said power became a big issue, particularly at the 90 nm node “when power consumption went up so fast.” Although strained silicon, power rails, sleep modes and multiple threshold voltages have kept Nvidia’s 20 × 20 mm die within a ~130 W power envelope, the big concern is leakage current. “DC power has exceeded AC power for the first time,” Chen said. Leakage is such an important issue for Nvidia that its transistors now have a slightly higher threshold voltage than in the past, especially for the non-critical paths.
|Graphics processors are well suited to many-core architectures for processing vertices and pixels.|
|Leakage (DC) power is a major concern as scaling proceeds.|
“Over the next two technology generations we will get to 10 billion transistors easily,” Chen said in a speech to ~1200 IEDM participants Monday. “We need leakage to be almost zero, or at least to have leakage be undetectable.”
Chen zeroed in on vias, calling via deposition a major reliability concern. A chip with 3.2 billion transistors has 7.2 billion vias, a number “which exceeds the world population.” He called on the IEDM audience, and Nvidia’s main foundry vendor Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan), to deliver one defect per part per billion (1 DPPB). “We have to make all the vias work; it has to be defect-free.”
Variation is hurting the company’s business, which depends on binning. The normal practice is to bin the best chips to the ultrahigh-performance accounts, devices that hit the mean performance and operating voltage metrics to the notebook market, and slightly underperforming chips to desktops. “The problem if the mean of the variation shifts day to day, we lose all of our ultra and some of our mobile bin,” Chen said. “It creates a huge inventory of desktop chips, some of which we have to discard. This is really going to be a major problem at 28/22 and beyond. Even 1 nm variation in a CD can affect our products in a very significant way.”
|The number of vias on Nvidia’s newest GPU exceeds the current world population.|
Variability is closely related to reliability. Some failed vias impact yields, which is bad enough. But a much worse problem, Chen said, is when vias degrade over time, causing chips to fail in the field. “Our biggest issue is poisoned vias,” Chen said, adding that at the 40 nm node voids in the copper can cause some vias to eventually become open. “We need absolutely zero defects on the 7.2 billion vias so we don’t get returns from the customers.”
Chen’s speech included a call to “my friends at TSMC to give me more 40 nm parts,” and a plea for improved via defectivity. Dick James, a technology analyst at Chipworks (Ottowa, Canada), said via defects have shown up on ICs manufactured by TSMC. Chipworks has inspected products from graphics vendor ATI, now part of Advanced Micro Devices (AMD, Sunnyvale, Calif.). “The problem appears to be that when they cut a via, a residue of photoresist gets on the edge of the via, which creates a ring-shaped discontinuity in the metal,” James said. “The discontinuity could create electromigration issues. We’ve seen the same problem on the upper metal levels on the ATI chips we’ve studied. It creates a reliability failure mode.”
(TSMC later said any problems with vias on the ATI chip were “teething problems” that were quickly resolved. James said that the ATI graphics chips also came from early production runs. “Our part was quite early in ATI’s production and any report we do is inevitably only a snapshot of that production,” James said after IEDM concluded.)
A marketing manager at Chartered Semiconductor Ltd. (Singapore) said Nvidia is investigating silicon-on-insulator (SOI) technology, which Chartered and GlobalFoundries both provide. Nvidia joined the SOI Consortium (Boston) last summer. James of Chipworks said the buried oxide layer in an SOI substrate could reduce current leakage by blocking leakage from an active area to the bulk silicon. “SOI could take out a whole leakage mechanism,” James said.
Nvidia also needs through-silicon vias (TSVs) so that it can connect its logic transistors to DRAMs on a separate die. With 3-D interconnects, it can vertically connect two much smaller die. Graphics performance depends in part on the bandwidth for uploading from a buffer to a DRAM. “If we could put the DRAM on top of the GPU, that would be wonderful,” Chen said. “Instead of by-32 or by-64 bandwidth, we could increase the bandwidth to more than a thousand and load the buffer in one shot.”
Based on any defect density model, yield is a strong function of die size for a complicated manufacturing process, Chen said. A larger die normally yields much worse than the combined yield of two die with each at one-half of the large die size. “Assuming a 3-D die stacking process can yield reasonably well, the net yield and the associated cost can be a significant advantage,” he said. “This is particularly true in the case of hybrid integration of different chips such as DRAM and logic, which are manufactured by very different processes.”