IMEC targets design program at fabless/fab-lite, foundries, EDA vendors – 10/5/2009 – Electronic News
The nanoelectronics and nanotechnology research center launches an industrial affiliation program on designing with emerging technologies.
By Suzanne Deffree, Managing Editor, News — Electronic News, 10/5/2009
IMEC today announced it has launched the industrial affiliation program (IIAP) INSITE (Integrated Solutions for Technology Exploration), a framework of design exploration modules that it said allows fabless and fab-lite companies, foundries, and EDA vendors to develop design and product information using emerging IC process technologies one to three generations ahead of IC manufacturing.
INSITE can be used to design in both IMEC’s emerging process technologies developed within its core CMOS research program and in more imminent foundry-level technologies targeted to early product development.
The INSITE program addresses two trends that IMEC said are creating a growing knowledge gap between the producers and users of digital CMOS technology: the move away from integrated design and manufacturing to separate chip foundries and fabless design houses, and the evolution toward more application-specific technology offerings as technologies need to be adapted to achieve the targeted chip specification as improved speed, power, area, and cost cannot be realized with the same technology.
“While the questions of fabless and fab-lite companies related to designing with emerging technologies are distinct from those of foundries, EDA companies and IP vendors, the solutions to their questions require collaboration and dialog between all parties,” Phillip Christie, principal researcher at IMEC, said in a statement. “INSITE will leverage IMEC’s extensive process technology knowledge and long tradition of working at the interface between technology and design. It will provide customized solutions for the exploration of design and technology trade-offs to all players in the semiconductor value chain.”
IMEC described the program as one set up as a modular and extensible framework that provides the required flexibility for the program partners. It comprises a design interface, circuit-level IP generation, and pathfinding.
The key competences of the framework are:
-An in-depth understanding of advanced process technologies and process integration;
-Fabrication and measurement of test circuits using IMEC’s 200-mm and 300-mm wafer facilities;
-A flexible design interface to quickly couple technology advances to design flows;
-The rapid implementation of circuit-level IP;
-Tools and flows for rapid design of pathfinding experiments.
IMEC said the design interface is fully compatible and shares the same standards as design interfaces from commercial foundries.
New technologies will be embedded into circuit level IP using industry-standard data formats to make certain that products can be synthesized using emerging technologies within standard design flows in a transparent way. For emerging technologies, IMEC said that the same library IP can be implemented as virtual libraries with limited layout information and imported into a design flow emulation environment for rapid scenario analysis.
In other news from IMEC, the nanoelectronics and nanotechnology research center last week claimed a major step toward 3D integration of DRAM on logic when it announced it and partners taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC.