TSMC’s VP R&D, Jack Sun, looks at the future of foundry/design-team relationships « Solido Design Automation

TSMC’s VP R&D, Jack Sun, looks at the future of foundry/design-team relationships « Solido Design Automation.

TSMC’s VP R&D, Jack Sun, looks at the future of foundry/design-team relationships

Helping chip design and process development move forward

By Ron Wilson, Executive Editor — EDN, 6/26/2008

Original Article: link

As the pivotal player in the CMOS-foundry industry, TSMC (Taiwan Semiconductor Manufacturing Co) occupies the leading edge not only in advanced-process market share, but in process development and the rapidly evolving art of building relationships between foundry engineers and chip-design teams. TSMC’s vice president of research and development, Jack Sun, is in the perfect place to watch both parties in this increasingly complex dance as they strive to outmaneuver the growing complexity of CMOS processes. EDN asked Sun what he sees as the foremost problem facing the foundry-design relationship today.

Sun answered quickly. “The primary problem today, as we take 40 nm into production, is variability,” he says. “There is only so much the process engineers can do to reduce process-based variations in critical quantities. We can characterize the variations, and, in fact, we have very good models today. But they are time-consuming models to use. So, most of our customers still don’t use statistical-design techniques. That means, unavoidably, that we must leave some performance on the table.”

Sun went on to describe a number of measures that TSMC engineers and customers are taking to reduce the amount of performance chip designers must give up to guard-banding. To begin with, he says, TSMC has consistently made decisions in choosing its process architectures to make things simpler for chip designers. One such decision was the choice—despite considerable capital and development investment—to move to immersion lithography. Immersion has significant benefits for the foundry. But it also means that TSMC can deliver—other variables being equal—more consistent shapes and accurate lithography simulation. “We can pretty accurately predict the actual shapes of features on the silicon now,” Sun says. “That means that extraction tools can more accurately predict transistor performance [and] circuit and parasitic impedances. And we don’t have to leave too much on the table to allow for unexpected variations in shapes and dimensions.”

Another key choice, Sun maintains, was the decision to stay with a conventional silicon-gate, silicon-oxide-dielectric gate stack. “We were able to stay with a structure our customers are used to,” Sun says, “and still achieve leadership in power density. Our non-high-k process is rivaling competitive high-k processes.”

But this choice meant that the foundry had to take other steps to increase performance. Sun says that the 40-nm process required scrupulous design work to eliminate excess gate capacitance, further wrestling with contact resistance, and a substantial increase in strain on the channels. “At this point, we are about running out of room for strain structures on the transistor,” Sun admits. Feature density and the fact that the impact of strain on channel mobility is orientation-dependent have required TSMC to require fixed-pitch patterns in dense areas and to enforce unidirectional channel orientation.

Another key area in making the process usable for chip designers is modeling—creating not just accurate models, but also the process controls that reduce variations enough to make the models meaningful. Sun says that baseline transistor models are still adequate—at least for the 40-nm, baseline transistor models. Substrate modeling, however, creates extremely complex nets and requires a huge amount of silicon validation, making it a more complex issue.

Sun highlights the issue of advanced process controls. “TSMC uses both feed- back and feedforward control loops and gathers a huge amount of data. We do a lot of, if you will, data mining to find the best knobs to tweak to control process variables,” he says. “We have so much experience with this now that we are tantalizingly close to being able to do an expert system for process centering.” In one case, TSMC had established an integrated link between its advanced process-control system and the chip-design partner’s database. “It’s a new concept we are trying,” he explains. “For most partners, we provide data in the form of process sensitivities, so the partners can update their test procedures to look for the things that we know can vary.”

In the absence of statistical tools, TSMC must also work to develop process corners that accurately reflect the vastly more complex patterns of variations happening across wafer lots. “We try to find ways to lump parameters together to simplify the corners,” Sun says. “But there are, for instance, layout-dependent stress effects. It’s a pain you have to live with. The best we can do is to provide accurate Spice models and restrictive design rules that will reduce the variations.”

The ultimate weapon in controlling process variations, Sun emphasizes, is not some magic bullet to make the variations go away or magic tool to make them invisible but, rather, a close partnership with design teams to allow them to design with the variations.

“Early adopters—companies like Qualcomm and Altera, which are already on 40 nm—have very early and deep collaboration with the process team,” Sun says. “As the process matures, we see a second wave of design teams. These teams still require collaboration, maybe for specific customized features, but otherwise they are working with a proven process and far less uncertainty.”

Even though this phased approach describes most collaborations, RF and precision analog designs still represent something of an exception. “RF and analog design have art to them,” he says. “The degree of collaboration that actually happens between the design team and its foundry depends on the sensitivity of the design team.” Some designers want all the help they can get, Sun suggests, whereas others don’t want anyone from outside the team to see—let alone participate in—what is happening within the design team’s inner circle. “This [reluctance] can really hinder collective learning,” Sun says, “but you have to respect the needs of the designers for differentiation. I think, though, that there is room to improve the model while respecting that. A lot of designers have their own secret sauce. But if the collaboration is not open, you end up leaving the optimizations undone.”

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One Response to “TSMC’s VP R&D, Jack Sun, looks at the future of foundry/design-team relationships”

This is a great article and we’ve pulled out some quotes and presented our views.

1. Sun answered quickly. “The primary problem today, as we take 40 nm into production, is variability,” he says. “There is only so much the process engineers can do to reduce process-based variations in critical quantities. We can characterize the variations, and, in fact, we have very good models today. But they are time-consuming models to use. So, most of our customers still don’t use statistical-design techniques. That means, unavoidably, that we must leave some performance on the table.”

>> Solido observed early on that the foundries are building sophisticated models which included variation parameters, but the customer base did not have the tools necessary to utilize these models easily. This is one of the fundamental gaps that Solido is addressing.

>> Solido has built a scalable and extensible platform upon which a variety of applications can be deployed to solve current and future process variation challenges. The Variation Designer platform and the Statistical applications package are available now. This solution enables designers to eliminate design losses resulting from over- and under-design without sacrificing efficiency and productivity.

2. In the absence of statistical tools, TSMC must also work to develop process corners that accurately reflect the vastly more complex patterns of variations happening across wafer lots. “We try to find ways to lump parameters together to simplify the corners,” Sun says.

>> Solido has developed a True Corner design flow that builds upon the process corners that TSMC provides. Designers can use Solido’s True Corner flow, which is similar to the very familiar process corner based design flow, to fix problems caused by statistical variation. True Corners are design specific and represent global, local and environmental variation. Designers can use these True Corners to ensure that they achieve a design that will meet or exceed specifications, with minimized power/area and maximized yields in a shorter time than is possible with a traditional design flow.

3. “But there are, for instance, layout-dependent stress effects. It’s a pain you have to live with. The best we can do is to provide accurate Spice models and restrictive design rules that will reduce the variations.”

>> Solido’s Well Proximity Solver application will address this specific problem. This application will enable a designer to determine the effect of well proximity on performance during the circuit design phase and to subsequently provide layout guidelines, thus eliminating expensive iteration cycles. It will also allow the designer to eliminate excessive guard-banding which can result in area penalties. Additional applications that will solve for other layout dependent stress effects will be developed as part of our roadmap.

4. “Early adopters—companies like Qualcomm and Altera, which are already on 40 nm—have very early and deep collaboration with the process team,” Sun says. “As the process matures, we see a second wave of design teams. These teams still require collaboration, maybe for specific customized features, but otherwise they are working with a proven process and far less uncertainty.”

>> Solido is actively engaged with early adopter companies, to solve variation challenges at newer nodes. Solido will collaborate with early adopter companies to develop leading edge applications. Solido is able to encapsulate this interaction and learning into tools that can be used by design teams that will adopt these nodes later in the process lifecycle.

5. Even though this phased approach describes most collaborations, RF and precision analog designs still represent something of an exception. “RF and analog design have art to them,” he says. “The degree of collaboration that actually happens between the design team and its foundry depends on the sensitivity of the design team.” Some designers want all the help they can get, Sun suggests, whereas others don’t want anyone from outside the team to see—let alone participate in—what is happening within the design team’s inner circle. “This [reluctance] can really hinder collective learning,” Sun says, “but you have to respect the needs of the designers for differentiation. I think, though, that there is room to improve the model while respecting that. A lot of designers have their own secret sauce. But if the collaboration is not open, you end up leaving the optimizations undone.”

>> Solido has committed itself to this collaboration model. We are engaged with various foundry groups and expect to forge deeper engagement on new technologies and related variation design challenges. We are engaged with leading-edge customers. We are integrating and collaborating with other EDA vendors to ensure the end solutions fits in seamlessly into the customers design flow.

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