Technology@Intel · A look at the future of the transistor from the Solid State Devices and Materials Conference (SSDM)
A look at the future of the transistor from the Solid State Devices and Materials Conference (SSDM)
I’m writing this on the plane from Narita airport to Portland as I return from giving the plenary talk at the Solid State Devices and Materials conference (SSDM), in Sendai Japan. It is always exciting to visit these device conferences to see the myriad of new options that are being discussed for next generation transistors.
Before I get into the technical details, I have a few fun stories to share about my trip. I arrived a little early, so I could have the weekend to tour Tokyo. Much of my time in Tokyo was spent figuring out the subway/train system. In all the excitement, I managed to lose my wallet on the subway, and to my surprise and delight – it was returned a few hours later (with all the money intact). I was deeply impressed as I doubt that would happen in New York! Another adventure was with a Japanese toilet at Tokyo institute of technology. Japanese toilets are quite complicated (among other things, they play music) with a number of interesting features (which I will not describe here, you’ll need to go to Japan to check). This was one of the more complicated ones, and in looking for the flush button, I pushed a green button that looked reasonable. Well, it was an alarm button. A horn sounded, the lights turned on and off and so on and so on. Made me deeply suspicious of all buttons for the rest of the trip. At this point, I hoped my adventures were over, but no. I had a most interesting night on the 12th floor of the hotel when the typhoon Melor passed over (as a side note, I began to feel jinxed, because I ran into Melor a second time when in California a few days later after it had crossed the Pacific).
Anyway, enough of the light stuff, now let’s discuss the meat! SSDM is a big conference (~1000 people) where the various conference sessions include papers ranging from energy systems to organic semiconductors. Of the most interest to me were the sessions focusing on the various approaches for continued gate scaling through improved short channel control.
High-k metal gate is the primary path for improved short channel control. Intel leads the pack in this area, with its recent 32nm announcement demonstrating successful second-generation high-k metal gate (http://www.intel.com/technology/architecture-silicon/32nm/index.htm). Note that much of the industry is trying to “catch up” to Intel, with significant discussion industry-wide on the correct architecture for the gate (gate-first or replacement, one metal or two, and so on) with representative SSDM papers such as those presented by Drs. Ikeda, Kim and Fukutome. There is also significant research on gate materials, shown with papers such as those from Drs. Kadoshima and Inumiya. Another area of strong research is fundamental physics of the HiK-metal gate materials system, with SSDM papers such as those by Drs. Hsieh and Shimizu.
Advanced device architectures are another path for improved short channel control. This include ultra thin body (UTB) devices, vertical thin body devices (for example, trigate and Finfet), and lateral nanowire devices. UTB devices are the simplest of the new architectures, with short channel control offered by a thin body, and with fabrication being an extension of historical processing. An additional advantage of UTB devices is excellent random variation due to the undoped depleted body (several interesting SSDM papers in this area, including the papers of Drs. Andrieu and Lee). The problem is that UTB devices are expensive (SOI is NOT cheap), and quite sensitive to variation in the body thickness (changes in body thickness affect VT from quantum effects, and also impact DIBL and SS)). In addition, the thin body creates high external resistance and makes it extremely difficult to strain the devices.
Multiple gate (MuGFET) devices such as FinFETs or Trigates are a longer term path for improved short channel control. These devices mitigate many of the variation issues with UTB devices (because the desired fin width is greater than 2X of the equivalent body thickness in an UTB device.) HOWEVER, the non-planarity of these devices represents significant challenges in fabrication. Dr. Veloso’s paper nicely explored many of these challenges in some detail. Lateral nanowire devices are next in the logical sequence, again offering significant advantages for short channel control, but at the cost of challenging fabrication. While nanowires offer further short channel benefit, they have all the issues of FinFETs, along with a host of new issues, many of which were explored in papers from Drs. Chen, Seike, Lee and others.
I had a lot of fun, and learned some new things. As a wonderful closure for the trip, as we were leaving Narita airport (after pushback and just as the plane started to taxi on its own) all the line service folks (the people who fuel the plane etc.) lined up and waved and then bowed the plane off. “What a wonderful custom,” I thought, as I waved back.