Risks of customer-owned tooling send designers to ASICs
Like do-it-yourselfers who wished they had called the plumber or electrician instead of botching a home repair, chip makers seem to be having second thoughts about customer-owned tooling (COT). COT’s vaunted advantages in cost and chip performance notwithstanding, the traditional ASIC flow appears to be making a comeback, according to at least one industry study.
“COT vs. ASIC really is a question of how much are you willing to risk,” said Bryan Lewis, semiconductor analyst at Gartner Dataquest. “If you adopt a COT flow and you blow one design, it can possibly lead to the end of your company. Most companies aren’t willing to take the risk and would rather hand off their design to an ASIC vendor.”
Lewis said that preliminary figures from a new Dataquest study show that COT flows produced 22.7 percent of ASIC designs this year, vs. almost 24 percent in 2001. The traditional ASIC flow picked up the slack, accounting for 60 percent of the ’02 designs, against 59 percent last year.
With more companies going fabless, with newer EDA tool flows tying logic design to physical design, with numerous physical-design engineers looking for work, and with foundries screaming to fill capacity, it would seem that this should be the heyday of what is essentially the semiconductor equivalent of do-it-yourself. In a COT flow, chip houses do their own logical and physical design, and then hand GDSII design data to a foundry. In an ASIC flow, customers do as much or as little work as they care to, and hand off the rest of the design to the ASIC vendor, which produces the chips and – more important – shoulders responsibility for making sure the design will function correctly in silicon.
COT and its accompanying design-services businesses have been picking away at ASIC market share since the mid-1990s, said Lewis. But he said the latest information compiled by Dataquest indicates the ASIC model reversed that trend in 2002. This year, he said, COT and design services will be flat.
Ronnie Vasishta, VP of technology marketing at LSI Logic Corp., said that this year the Milpitas, Calif. ASIC maker is witnessing a return of customers that tried out a COT flow and found it not to their liking. “And we’re hearing that boards of directors of new companies are recommending that their design groups go with safer ASIC flows, because the risk is too high in a COT model,” said Vasishta.
Process geometries of 130nm, 90nm, and 65nm will crank up that risk, ASIC vendors maintained, sending even more chip designs back to the safe haven of ASICs. As new processes come online, they said, the accompanying physical effects such as crosstalk, inductance, and IR drop appear too perilous for customers to handle on their own.
Moreover, said Vasishta, some customers failed to foresee the size of the investment needed to adopt a COT flow. Resources must go into hiring physical-design engineers, buying expensive back-end tools such as place and route, and then stitching together tool flows, doing packaging and performing tests. Especially given the rough economy, ASIC vendors said, many companies are not willing to make that kind of investment, let alone embrace the risk level associated with COT.
Still, the lure of COT is strong. James Hines, foundry analyst with Gartner Dataquest, said that many chip makers are drawn to the COT model because it has proven to offer some companies, such as graphics-chip maker Nvidia Corp., a heady mix of silicon-cost savings, higher performance and smaller die size than an ASIC engagement could.
That’s one reason the COT-to-foundry model of chip making has been pulling away market share from the traditional ASIC market for several years. The foundry business itself grew into a $10 billion industry last year, Hines said, accounting for 17 percent of the overall semiconductor market. Early adopters like Nvidia have shown they can rule a high-performance niche with superfast time-to-market demands with COT.
Hines noted that the per-part price is typically much cheaper for chip designs that go straight to a foundry than at an ASIC vendor. For lower-volume orders, ASIC makers typically charge nonrecurring-engineering fees for doing physical design, verification, test, and packaging. Foundries, too, require a minimum silicon engagement. However, “the bottom line is, silicon performs better and typically is cheaper using a COT-to-foundry model,” said Hines.
Tom Reeves, VP of the ASIC group at IBM Microelectronics, agreed that when companies need chips quickly, a COT flow will typically beat out ASICs in terms of chip performance. But he said, ASIC vendors are very flexible if the price is right, and many have semi-custom design teams or layout “A teams” that will maximize performance of a design, assuming the customer has allocated enough time for it.
Moreover, ASIC vendors said, no chip is cheap if it doesn’t work right on the first pass. Indeed, the biggest selling point of the ASIC flow is peace of mind.
The tool equation
As design tools have grown more capable and automated, and process technology more standardized, engineers have taken a more hands-on approach with their designs, lessening the need to hire ASIC companies to do it for them. In the glory days of the ASIC business, the early 1980s, systems companies would hire an ASIC vendor to do an entire design – sometimes an entire system – turnkey, and never had to sully their hands with transistor-level design or other inner workings of the device. In return for this service, they would pay for design NRE as well as silicon.
With the rise of cell-based design in the mid-’80s customers became more design-savvy and started developing the front end of their ICs themselves, handing gate-level netlists to ASIC vendors for the “black magic” – physical design, verification, test and, ultimately, a packaged chip. Doing some of the design in-house saved on NRE costs.
Then, in the late ’80s, semiconductor companies started using common fab equipment and processes instead of proprietary ones. This allowed EDA vendors to start offering standard-cell place and route tools that worked better than many of the proprietary tools from ASIC makers’ CAD groups. Gradually, ASIC vendors too gravitated to the commercial products and whittled down their own tool groups.
The rise of pure-play foundries in the mid-1990s helped demystify the traditional ASIC business model even further by offering standard silicon processes and, thanks to library vendors like Artisan Components Inc., the libraries needed to create designs in cutting-edge silicon processes. And the silicon was cheaper.
These factors gave rise to the COT business model, in which fabless chip houses and even systems companies could conceivably buy physical-design tools from an EDA vendor, create a design up to GDSII and pass it on to a foundry with no middleman.
Integrated device manufacturers (IDMs), which use a COT flow and pass designs to foundries like TSMC, UMC, and Chartered, are a growing part of the pure-play foundry business. TSMC last quarter, for example, counted 35 percent of its revenue from IDMs. However, Dataquest’s Lewis said that system companies adopting a COT flow represent a small market that is getting even smaller, shrinking from 5 percent to 2 percent of the overall silicon market in the rough economic climate of 2002.
The foundry-to-COT flow has opened a potentially huge new user base for EDA vendors. Cadence, Synopsys, Magma, and Monterey Design are feverishly trying to put together all-in-one flows that will take a design from register-transfer level to GDSII.
But while “the design gap is indeed a real issue,” the “all-in-one, front-to back solution” is not here yet, said Vasishta of LSI Logic. ASIC vendors can’t rely wholly on commercial tools. “Today we buy most of our tools from EDA vendors, but we and every ASIC vendor have to supplement our tool flows with our own tool development.”
Not wanting to step on the toes of the ASIC houses that are their biggest customers, EDA vendors don’t say it too loudly, but they believe that as these comprehensive flows mature, they will likely enable more systems companies to do their own physical design.
For their part, design-services companies and library vendors, the other legs propping up the COT flow, are more than willing to educate users on the advantages of COT. Artisan Components, for example, offers engineers a COT design class.
ASIC vendors for the most part are not fighting the COT model and are embracing the use of pure-play foundries. LSI Logic decided last year not to innovate 90nm silicon but to let Taiwan Semiconductor Manufacturing Co. cut its teeth on the latest manufacturing processes. LSI Logic will then buy the process and equipment from TSMC as the process hits mainstream use.
IBM too has expanded into the foundry business and, like TSMC, said it welcomes any model that users want to adopt, as long as there is money for silicon involved.