IEEE Spectrum: Packaging: The Red-Headed Stepchild of the Semiconductor Industry
POSTED BY: Sally Adee // 화, 12월 15, 2009
The time honored trope of teen movies is the mousy nobody who finally takes off her glasses and lets down her ponytail, and suddenly she’s the prom queen. In the semiconductor industry’s version of that movie, that girl’s name is Packaging.
Packaging was the undercurrent of much of this year’s International Electron Devices Meeting. No one could have put it better than Semiconductor Industry Association vice president Pushkar Apte, who stated that “packaging is the red-headed stepchild” of the industry. Until now, anyway. Two major forces are driving the attention back to packaging: Medical applications and the end of scaling.
As an example of the former, at IEDM, Purdue University researchers showed implantable wireless transponders that can monitor radiation doses received during cancer treatments. The miniature transponders would be implanted near a tumor during radiation therapy. The part is a prototype, as far as I understand, and the Purdue researchers are working with the radiation oncology department at the University of Texas Southwestern Medical Center. There, doctors can give them an idea of what’s needed in terms of packaging. But what happens when a part like this transitions from prototype to off-the-shelf? It’s going to need innovative packaging. That’s what.
The second driver is the ever-impending end of Moore’s law. It’s no secret that engineers are running out of options with transistor scaling. The industry is nominally at the 32nm process—which means Intel is about to start shipping microprocessors with 32-nm feature sizes. No one else is. (Intel will soon release their 32-nm processor, called Westmere.)
But other chipmakers are struggling to keep up with that roadmap. AMD only released its first 45-nm processors this past January. According to EETimes, “a period of more than two years is now expected between the introduction of AMD’s 32nm technology and the previous 45nm node first seen in late 2008.”
TSMC is also lagging behind Intel but ahead of AMD with 32-nm process technology, which it expects to have ready in 2010. (For more on where everyone stands with 32-nm process technology, read this exhaustively researched EE Times piece.)
Why is it so hard to scale? Researchers agree that the industry has hit a brick wall because scaling transistors to ever-tinier dimensions causes reliability to fall steeply. Researchers who didn’t want to go on the record told me, and at a short course on Sunday, attendees repeatedly expressed frustration at the difficulties of further scaling.
3D integration looks like a viable alternative for chipmakers who don’t want to bang their heads against Moore’s law in the quest for 22-nm process technology. 3D integration boils down to this: stack ’em vertically instead of squeezing more and tinier transistors on a planar surface. It means that with a fixed transistor and die size, you can still add processors and memory. Johns Hopkins University electrical engineering professor Andreas Andreou estimated that by the time the industry arrives at 22-nm process technology, it would be more effective to stack four 22-nm chips than press on to the 11-nm node.”The gold rush of shrinking will be replaced by 3D,” he predicted.
Even Nvidia is on the 3D bandwagon: John Chen said in his keynote presentation that graphics processors can’t make progress unless they go 3D. Two IEDM sessions were devoted entirely to advanced 3D technology and processing for memory and logic. In one session chaired by researchers from IBM and Samsung, CEA-LETI researchers threw down the gauntlet: For the first time, they said, 3D CMOS integration can be considered a viable alternative to sub-22nm technology nodes. TSMC researchers positioned 3D integration as healthy competition for the 28-nm node. IMEC, Fujitsu, and ST Micro presented their research into making 3D work.
Researchers are divided on the severity of the issues that plague 3D integration: heat, alignment, and metal contamination still remain, but according to Hopkins professor Andreou and NEC researcher Yoshihiro Hayashi, heat is a red herring: any number of innovations will easily solve the heat problem by the time 3D packaged wafers are ready to hit the shelves (among these, using through-silicon vias to transport the excess heat to the heat sink, but that’s a whole other story).
In any case, the general assumption is that you can work around the Moore’s law limitations by doing other things, like 3D integration. At the very least, 3D chip integration might buy the industry a little time so that researchers can get their ducks in a row with promising technologies like extreme ultraviolet lithography, multigate transistors, and 2nd-gen high-k metal gate technology.
But we’re not at the prom yet. (We’re still watching the part of the movie where the best friend realizes that our girl Packaging needs a haircut and a full face of makeup.)
You’ll note that most of the problems researchers described are about packaging. Many ingredients in 3D stacks rely on innovations in packaging to make them viable. To solve the heat problem, for example, researchers are assuming that new ways of diverting excess heat to the heat sink will be developed. But who’s going to figure that out? Are through-silicon vias part of the chip or part of the packaging? What about those heat sinks?
3D chips require new kinds of packaging. And new kinds of packaging require innovation. And that, at last, is the crux of the problem: innovations in packaging? Whose problem is that?
The semiconductor industry has disintegrated, over the past decades, into many horizontal layers. Consider how the chip in your laptop got there. A designer at a fables semiconductor company probably designed it and then sent it to TSMC. TSMC manufactured the chip based on those designs and sent it to the packaging company, which packaged the chip and sent it to the systems guy, who put it all together and sent it to its final destination, the end unit provider.
Now companies are finding that they need to re-integrate at the leading edge. Some fabless companies have said that in order to get the packaging they want, they need to invest in packaging startups.
That disintegration/reintegration dynamic raises a question: who across these companies has ownership, with all the rewards and liabilities that word implies? If packaging becomes more important and plays a bigger role in chip design and innovation, it will needs to address, particularly for medical applications, issues of heat, reliability, and safety.
The packaging industry as a whole sees about $20 billion in revenue each year. Contrast that with Intel alone, which pulls down $40 to $50 billion a year. Additionally, chipmakers on average pump almost 20 percent of their income back into R&D. Contrast that again with R&D spending by packaging companies. ASE–the biggest packaging behemoth, which brings in about $3.5 billion a year–is the record holder among its cohort for how much it spends on research and development: 3.2 percent. 20 percent of $40 billion is a lot, and that’s probably why Intel is going to be the first to ship 32-nm processors. 3.2 percent of $3.5 billion? Well, it’s not enough for any kind of risky, out-of-the-box innovations. The industry is just going along to get along.
Who can blame them? Why should they absorb the risks that will plague any kind of innovation in packaging? Innovation in packaging also implies liability. Just look at what happened to Apple last year when Nvidia famously screwed up its GeForce GPUs. Apple had to replace the faulty chips for free. The problem was traced to a packaging defect.
Microsoft had to write down its first Xbox chips because of packaging issues that led to the infamous “red rings of death“– to the tune of $1 billion.
And if you’re still not convinced, think about the potential liability in medical implants.
Right now, no one is in a position to be responsible for innovation in packaging, but innovation is sorely needed. Someone needs to step up and give this poor girl a makeover.