EETimes.com – ISSCC: Intel has edge over AMD, for now
SAN FRANCISCO, Calif. — Intel Corp. has a significant, if temporary, edge over archrival Advanced Micro Devices based on news and papers emerging here Monday (Feb. 8) at the International Solid State Circuits Conference (ISSCC).
Intel described at ISSCC its first 32nm server processor to use six cores. Meanwhile AMD discussed a new core it will use in its first processor to combine x86 and graphics cores called Llano.
Separately, Intel announced Monday its long-delayed Itanium 9300. It is Intel’s first Itanium chip to use the company’s QuickPath Interconnect letting OEMs link eight multicore processors with additional logic. To date, AMD has been limited to linking four chips in a symmetric multiprocessing system without the need for extra chips.
Intel’s Westmere EP is a 32nm server CPU using six dual-threaded cores linked to DDR3 memory. It leapfrogs AMD’s existing 45nm Istanbul server chip, launched in June that uses six single-threaded cores and links to DDR2 memory.
Intel said it will roll out in 90 days an eight-core server chip, Nehalem EX, made in a 45nm process. AMD is expected to respond later this year with a 12-core CPU called Magny Cours. It will put two six-core die in a package that links to DDR3 memory.
Intel’s six”core Westmere packs 1.17 billion transistors, uses a 12 MByte shared L3 cache and supports low-voltage DDR3 memory. Intel’s ISSCC paper describes a new anti-resonance feature in Intel’s QuickPath Interconnect that lowers jitter on the chip.
Meanwhile, AMD is providing only a few details about Llano, a version of its 45nm x86 core upgraded for use in the company’s first processor to merge x86 and graphics cores. Llano will use four x86 and one graphics core, link to DDR3 memory, sample this year and ship in PCs in 2011.
Intel showed a working version of its first Westmere processor at last year’s ISSCC. That chip combines separate 45nm graphics and 32nm x86 cores in a single chip package and is shipping in systems now. Intel has said it will put graphics and x86 cores on a single die with a 2011 chip that uses its next-generation microarchitecture called SandyBridge.
AMD revealed the x86 core in Llano measures 9.69mm2 and uses 35 million transistors, excluding a Mbyte L2 cache block. It will run at up to 3 GHz and operates across a 0.8 to 1.2 V range while dissipating up to 25W. It is made in a 32nm silicon-on-insulator process.
In its paper, AMD detailed power saving techniques used in the core. They include use of a novel NFET power grating transistor and a clock grid optimized to reduce clock buffers and clock switching power. AMD did not talk about the graphics core used in Llano or any other details of the processor beyond its core.
The Llano x86 core is an anomaly of sorts. Most of AMD’s future CPUs will employ one of two new x86 cores, called Bobcat and Bulldozer. The company so far has not revealed many details about those cores expected to emerge in products starting in 2011.
The new AMD cores will compete with the SandyBridge 32nm microarchitecture Intel will likely reveal late this year. The new cores will set up the next round of leapfrog between the two archrival’s products.
Separately at ISSCC, Intel also described new low power circuits used in its Westmere device that includes two x86 cores and one graphics core. The chip uses low voltage DDR3 links running at up to 1.3 GigaTransfers/second with new fast wake up circuits. It also applies new power management techniques to the graphics core that runs from 150 to 500 MHz and to analog circuits on the chip.
Intel will also present a handful of papers on research efforts exploring more aggressive multicore architectures.
One paper describes a 45nm device that uses 48 Pentium-class cores on a message-passing network. It marks a step forward from a chip the company discussed at previous ISSCC sessions using 80 cores that were essentially floating-point units, not full x86 cores.
A second paper presented Monday discusses an 8×8 mesh network on a chip that delivers 2.6 Terabits/s in throughput using a circuit switched technique. The approach aims to save power by setting up direct point-to-point links across a chip, eliminating buffers.