TSMC’s Chiang Sees History on Side of Gate-Last High-k Approach – 2010-02-10 16:40:37 | Semiconductor International

TSMC’s Chiang Sees History on Side of Gate-Last High-k Approach – 2010-02-10 16:40:37 | Semiconductor International.

TSMC’s decision to adopt a gate-last approach to high-k deposition was informed by history, said S.Y. Chiang, in charge of R&D at the foundry. Two decades ago, companies tried to use the same gate electrode for both N- and PMOS transistors, a method that was soon abandoned, Chiang said. After a series of face-to-face meetings, TSMC’s design rules for its high-k process are being accepted by its largest customers.

David Lammers, News Editor — Semiconductor International, 2/10/2010

Last summer, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) made a surprising decision to use a gate-last deposition method for the high-k/metal gate stack of its 28 nm transistors. TSMC’s decision to use a replacement metal gate (RMG) technique was guided by history, said S.Y. Chiang, the senior vice president at TSMC in charge of R&D.

S.Y. Chiang (021010-ShangYiChiang.jpg)S.Y. Chiang, senior vice president, TSMCTwo decades ago, the semiconductor industry went through a similar tussle, when early CMOS developers tried to use an N+ poly gate for both the N-channel and P-channel devices. “When the industry began to do PMOS, companies found an N+ poly gate doesn’t work well,” Chiang said. “It was difficult to lower the Vt, so some people tried to add a counter dopant into the active region of the silicon channel to try to match the Vt. That caused a lot of problems, and made gate control and SCE (short channel effects) much worse.”

The gate-first approach to high-k ran into similar Vt control problems, Chiang said. Efforts to use capping layers improved gate-first performance, but a gate-first cap-layer process “gets very, very complicated and difficult to do,” he said. Two decades ago, for one technology generation, companies also tried to adjust the Vt for both NMOS and PMOS. “We went through exactly the same step when in our history we tried to use N+ poly,” Chiang said.

Asked about the restrictive design rules (RDRs) required for the gate-last method, Chiang said TSMC has been working with the layout teams at its largest customers to adjust to the gate-last high-k flow.

“With the gate-last technology, we do have some restrictions,” he said. “There is difficulty in planarizing it. However, if the layout team is willing to change to a new layout style, then they can get a layout density that is as good as with the gate-first approach. Not better, but the same. And it is not that difficult.” With high-k, Chiang added, “everybody — the process people as well as the layout people — need to adjust the way they do things in order to make the products competitive.”

TSMC’s design services team is working with the layout engineers at its largest customers. Chiang said they have demonstrated that with the appropriate alterations the IP cell libraries can achieve an equivalent layout density as with the gate-first approach. “Some people at first complained a lot, saying there would be a large density gap if they used the TSMC RDRs,” he said. “But after face-to-face meetings, the gate-last technique has been very well accepted.”

TSMC’s customers also appreciate what Chiang said is “a side effect” of using the gate-last approach: higher strain for the PMOS transistors.

TSMC plans to offer its first 28 nm processing by the middle of this year, using an SiON gate stack. “At 28 nm, that is the generation we push oxynitrides to the limit,” Chiang said. “We won’t continue to use oxynitrides after that — the transition has to happen somewhere.” The SiON process does have a cost advantage, and Chiang said customers who are not so concerned about gate leakage can move quickly to the 28 nm generation with the oxynitride process. “When it comes down to leakage, the customers who emphasize gate leakage have got to make the switch to high-k.”

TSMC high-k (021010-TSMCHKMG.jpg)TSMC will use its 28 nm SiON process to shake out issues not related to high-k/metal gate deposition. (Source: TSMC)

After the 28 nm SiON process moves into production at the end of the second quarter, TSMC will work to “clean off” any issues relating to interconnects, contacts, design rules and other issues. “That way, when we offer the HKMG process later in the year, we can be more focused on solving the HKMG process issues,” Chiang said.

Asked if the 28 nm generation promises to be a challenging one, Chiang said, “Some generations are relatively easier. For example, the transition from 90 to 65 nm had a very low risk. I do certainly believe 40 to 28 is very definitely a high-risk one, and we are preparing for that. We are preparing for all the possible scenarios. Reliability is a risk, and yield control. But we are working hard to prepare. Between 2006 and 2009, our headcount doubled, so I am pretty confident we will make this next generation a successful one.”

Chiang predicted the industry will coalesce around the gate-last method. “I do believe the gate-first people will change to gate last at the 22 nm node,” he said. “I am not criticizing them. But I think they will change. Unless they can find some very innovative way to adjust the threshold voltage without a lot of high cost, they will have to change.”

  1. Intel enjoys so called RMG (replacement metal gate) process at 45nm and now at 32nm. Intel confirmed that RMG flow is working for 22nm as well. The drawback of gate last process is clear that physical gate length scaling is limited due to narrow gap on the gate hole. Reducing gate height is also limited due to raised S/D.
    In situ doping method on raised S/D method could eliminate thermal issue for PMOS Vt issue. If gate first to turn to gate last at 22nm, I don’t think gate first folks will turn to gate last at 22nm, as gate last works until 22nm. With coming 3D transistor, gate first should be a better option for those already use gate first.

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