EETimes.com – Intel’s Gargini pushes III-V-on-silicon as 2015 transistor option

EETimes.com – Intel’s Gargini pushes III-V-on-silicon as 2015 transistor option.

LONDON — A presentation prepared by Paolo Gargini, Intel’s director of technology strategy, to give to the Industry Strategy Symposium Europe, held in Dublin, Ireland, earlier this week, stressed Intel’s progress in adding compound semiconductor layers to silicon as a means of continuing scaling and reducing power consumption.

Gargini, also chairman of the International Technology Roadmap for Semiconductors (ITRS), said in the presentation that the inclusion of III-V materials is a 2015 transistor option that could deliver either three times the performance of silicon at the same power consumption, or deliver the same performance as silicon at one-tenth the power consumption. However, integration of a thin compound semiconductor transistor channel with conventional silicon manufacturing would be the key to adoption.

While exceptional progress has been made in silicon to get to 32-nm, Gargini indicated in his slides that progress is coming only with more and more complicated additions to the basic silicon manufacturing process, such as the increased amounts of strain necessary to increase the electron mobility above its natural value; and the possible use of 3-D structures such as FinFETs.

Multigate FinFETs have advantages in improved electrostatics and a steeper sub-threshold slope, but Gargini put question marks against such things as parasitic resistance and capacitance and a layout methodology.

“Increase mobility in the transistor channel leads to higher performance and less energy consumption,” said Gargini on the slide, adding, “compound semiconductors have higher electron mobility than silicon; indium antimonide is highest of all.” Where gallium arsenide has 8 times higher mobility than silicon, indium arsenide is 33 times higher and indium antimonide is 50 times higher.

In the presentation Gargini laid out a few alternatives for integration. One method would be to include indium antimonide quantum-well FETs on a semi-insulating gallium arsenide substrate. Both depletion- and enhancement mode devices are possible.

As an alternative Gargini outlined progress in integrating an InGaAs quantum-well FET with a high-k dielectric gate stack. Gargini highlighted a series of papers presented by Marko Radosavljevic of Intel to the International Electron Devices Meeting (IEDM) over the years 2007 to 2009. This illustrated progress in developing the NMOS, PMOS transistors and, in December 2009, the high-K metal gate.

Gargini’s final conclusion was: “The advancement in non-silicon semiconductors deposited on silicon substrates could enable a new family of low power devices in the future.”

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