EETimes.com – Junctionless transistor is ready for 20-nm node, says researcher
LONDON — Professor Jean-Pierre Colinge of Tyndall National Institute (Cork, Ireland), co-author of the paper Nanowire transistors without junctions that was published by Nature Nanotechnology recently, has said that junctionless transistors could be implemented commercially at around the 20-nm manufacturing node.The junctionless transistor is based on use of control gate around a silicon nanowire. The gate can be used to modulate the resistance of the nanowire and to “squeeze” the electron channel to nothing, thus turning off the device. Doping is used to produce p- and n-type FETs but there are no steep dopant gradients nor junctions, which promises simplified manufacturing.
Such a major change in the structure of the fundamental electronic device could be expected to require a great deal of independent research. An introduction at or around 20-nm would require companies to switch more or less immediately. However, a switch to the junctionless transistor could fit in with previously forecast moves by the industry away from planar transistors and towards FinFETs and multi- and wrap-around gate structures.
Speaking to EE Times by telephone Professor Colinge said: “It’s not shown in the Nature paper but we have made a silicon nanowire measuring about 10 nanometers by 10 nanometers. Now there is a rule of thumb that the gate length should be about twice the nanowire dimensions to avoid short channel effects. I think junctionless transistors could intersect with ITRS [International Technology Roadmap for Semiconductors] at 20-nm.”
Professor Colinge continued: “The junctionless transistor could compete now but it will take time for semiconductor companies to get used to the idea. People are scared of the high doping levels.”
According to the paper published in Nature Nanotechnology dopant levels of between 2 x 10^19 and 5 x 10^19 atoms per cubic centimeter were used. The high doping levels are required to ensure a high current drive and good source and drain contact resistance, the paper states.
But Professor Colinge pointed out that the junctionless transistor scales far better than a conventional transistor which will need to implant and control complex dopant gradients and profiles in diminishing distances. “The junctionless device does scale better. You still need the high resolution etching but you don’t have to scale the gate oxide as aggressively as you do on a regular device,” he said.
He also said that while the most recent paper does not address the issue, there is no reason why silicon junctionless transistors should not be amenable to induced strain to increase electron mobility. At the same time the junctionless approach could also be applied to materials other than silicon. “Yes it is applicable to other materials such as compound semiconductors,” Professor Colinge said.
Another difference between a conventional transistor and a junctionless transistor is that the junctionless device is a normally-on device, although this is made more complex by use of doped gate materials, Professor Colinge said. But he stressed that for the purposes of logic, memory and small signal operation there is no difference to a conventional transistor. “So far as we know the devices are interchangeable and there are no implications for the layout of logic,” he said.
The research presented in the Nature paper was partly paid for by Tyndall’s participation in two European funded projects Nanosil and EuroSOI+.