Taking the road from ASIC to FPGA – 25/02/2010 – Electronics Weekly

Taking the road from ASIC to FPGA – 25/02/2010 – Electronics Weekly.

Guest columnist Tom Feist, director of tools marketing at Xilinx restates the arguments for considering FPGAs – no DFM, no mask prep, no DRC/LVS

If you’ve been in the electronics industry even just a short time, you’ve likely witnessed first hand the increasing adoption of FPGAs over ASICs and ASSPs for a growing number of applications from aerospace and defense to medical and industrial to automotive, broadcast and communications equipment.

With the introduction of each new silicon process technology ASICs and ASSPs are becoming more cost prohibitive and risky to produce and only feasible for a shrinking number of the highest volume applications. ASICs are rapidly going the way of the Dodo and the standard gate array.

With multi-million gate capacity, high-speed serial IO, large blocks of on-board RAM and DSP slices, today’s FPGAs are extremely powerful system-on-chips that are ideal for most applications. Even the smallest devices of our high volume line of Spartan-6 FPGAs are faster and have great capacity than the most advanced ASICs on the market just six years ago—the largest devices in our new Virtex-6 FPGA family boast performance, capacity and functionality that is greater than many of today’s mainstream ASICs.

With all this as a backdrop, we are seeing a growing number of engineering teams transitioning from ASIC into FPGA design teams. Many of these teams would like to leverage the tools, flows, and methodologies they’ve previously used or developed for ASIC design projects to their new FPGA projects. They often find that while the flows are similar in many ways, in other ways they quite happily different.

Those making the transition are often amazed and quite relieved by the fact that they don’t need as many tools and no longer have to account for the expense associated with advanced ASIC flows.

Because Xilinx already produced the FPGA silicon, design teams don’t have to run any tools that ensure the proper creation of masks or silicon features, such as hundred thousand dollar/pound DRC vs. LVS, design for manufacturing, or mask correct layout tools. In most cases, design teams will no longer need advanced IC signal integrity type tools because we’ve already accounted for those issues when we designed the silicon.

In fact, new converts to FPGA will be shocked to find out that the entire tools suite for FPGA design is lower in cost than an entry level ASIC-class HDL linting and debugging tool. And if they are a senior ASIC design engineer, they may even become tear eyed and misty with nostalgia as the FPGA flow is reminiscent of the days of the ASIC-handoff, in which designers spent the bulk of their time dealing with front end design (architecture creation, logic design and verification) and would hand off their design at logic synthesis to an ASIC vendor to do the physical design.

They’re even amazed at how much less time they have to spend on their design projects, especially in performing verification. Where a typical ASIC flow is 18 months, a typical FPGA flow for the largest FPGA devices is 8 months, often shorter. Where verification in its many forms consume upwards of 60 to even 75 percent of the overall ASIC development time, in the FPGA world it typically can consume only30% of overall design time. This is simply because in the ASIC world if a single error makes its way to production silicon, it can require a multimillion dollar respin and severe delay in production that can be devastating, even destroy a company. Therefore ASIC design teams spend considerable time trying to send flawless designs to the fab, only to have missed some critical functional or timing error. In FPGA, if you have a logic mistake, you can fix it and simply reprogram the FPGA—even after you’ve deployed the product in the field.

Users are also happy to find out that in the FPGA tool world, the old saying “you get what you pay for,” doesn’t apply too aptly to FPGA vendor tools. In fact, for the price, most users are extremely pleased with the functionality and breadth of FPGA tools that FPGA vendors produce for their customers. What’s more, FPGA vendor flows are relatively open and support interfaces to third-party tools, which allow users to add the tools of their choosing to their FPGA flows.

Today we’re seeing many of these teams adding high level co-design and verification commonly called ESL (electronic system level) tools and advanced logic verification tools to their FPGA flows. ESL tools allow designers to describe with system level languages the desired functionality of their entire systems (software as well as hardware), then test that functionality and once optimized move their architectural description to RTL and implementation in the FPGA. Today, there are several tools and flows using different languages that perform high level co-design and co-verification but no single de facto standard has emerged, as each of these tools thus far typically target a particular application rather than broad sets application spaces.

Another area that is maturing quite rapidly due in large part to the legacy of ASICs is advanced logic verification. Because a single mistake in ASIC code design can have such devastating consequences, EDA vendors at the urging of ASIC teams have developed highly advanced logic design flows that include assertion based verification and high level HDLs such as SystemVerilog. While Xilinx’s ISE Design Suite doesn’t yet include native support for AVB or SystemVerilog, many customers connect third-party simulation environments to ISE to effectively ensure their code is as clean as possible before programming their designs into the FPGA.

Of course, FPGA users have the enormous advantage of being able to program their design into their FPGA at any time and test not only the logic functionality of their FPGA but the overall functionality of their FPGA in the context of the their system. We provide an advanced tool in the ISE Design Suite called ChipScope Pro that is very useful in this silicon-in-system debugging. What’s great about this extra layer of verification is that it not only allows folks to identify issues with the FPGA but also the shortcomings of the rest of their system. What’s even better is that once you identify a system issue you can often add functionality to your FPGA design that will make up for the shortcomings of another (often unmodifiable) IC or discrete in your system.

Indeed, as more ASIC designers move to FPGAs, they are often quite surprised and pleased by how much more simple and faster and less stressful it is to program an FPGA than it is to design an ASIC. At the same time, we continuously learn from our customers (who are increasingly not only hardware designers but also embedded software and algorithm architects) and looking for ways to better our flows. If you haven’t used our tools or our FPGAs, I encourage you to give them a try by starting with our free Web Pack or 30-day free evaluation of our full ISE Design Suite.

Tom Feist is the Senior Marketing Director for the ISE Design Suite at Xilinx. He can be reached attom.feist@Xilinx.com

  1. No trackbacks yet.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s

%d bloggers like this: