Physical IP

  1. Memory IP
    • element for memory compiler and custom memory
      • Register files
      • SRAM
      • ROM
    • ARM memory IP for TSMC40G tech
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  2. Logic IP
    • Std cell library
      • combinatorial
      • sequential
      • multi Vt
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  3. Interface IP
    • DDR interface
    • PHY
    • GPIO
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  4. Functional block IP
    • CPU core
    • GPU core
    • USB
  5. System IP (AMBA in ARM case)
    • interconnect
      • Massive growth in system integration places on-chip communication and interconnect at the centre of system performance. Traffic interactions have become complex and, if left unchecked can cause poor, unpredictable system performance.
      • AMBA
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      • Technical features of the high-performance AMBA 3 AXI protocol include:
        • Uni-directional channel architecture. Information flow is in one direction only, enabling very simple bridging between clock domains. This reduces the gate count and hence timing penalty when signals traverse complex SoCs.
        • Support for multiple outstanding transactions. This enables parallel execution of bursts, resulting in greater data throughput. This facilitates both high performance when required, and low power as tasks complete in a shorter time.
        • Independent Address and Data channels. This enables per-channel optimization, by breaking timing paths as required to maximize clock frequency and minimize latency.
        • Increased flexibility. With symmetrical Master and Slave interfaces, AXI technology can be easily used for anything from point-point to multi-hierarchy systems.
    • memory controller
      • AMBA Dynamic and Static Memory Controllers provide the ideal interface to off-chip memory for systems with Cortex™ (A,R) and Mali™ processors
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