Gate First, or Gate Last: Technologists Debate High-k – 2010-03-10 15:41:15 | Semiconductor International.
David Lammers, News Editor — Semiconductor International, 3/10/2010
As high-k rolls out beyond Intel Corp.1 to both mobile and high-performance applications, the industry now faces a divided landscape.2 Intel and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) — the largest MPU provider and pure-play foundry, respectively — are backing the replacement metal gate (RMG) or gate-last approach. Their competitors — Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.), GlobalFoundries Inc. (Sunnyvale, Calif.), IBM Corp. (Armonk, N.Y.), and other members of the Fishkill Alliance — are using the gate-first approach, at least for the 28 nm node.3 United Microelectronics Corp. (UMC, Hsinchu, Taiwan) said it will use a hybrid approach employing a gate-last method for the more-difficult PMOS transistor.4
No matter what deposition flow is used, high-k is offering benefits, which is why the stakes are so high for getting it right. Not only does high-k sharply reduce gate leakage, the gate capacitance scales with a thinner equivalent oxide thickness (EOT). Though mobility may be not quite as high as in a chip using a native oxide, cutting the EOT with high-k enables a shorter gate length and improves the drive current.
However, pressure is building on the gate-first approach. Some high-k experts argue that the high-temperature steps following the high-k dielectric and metal gate deposition cause the Vt to shift, affecting PMOS performance in particular. Others, including John Pellerin, director of technology at GlobalFoundries, argue that the gate-first approach requires less-restrictive layout design rules, provides for a smaller die size, and eases IP porting, while meeting the performance needs of customers at the 32/28 nm node.
“We are unequivocally committed” to the gate-first approach at 28 nm, Pellerin said. “The die size and scaling potential are very critical factors. We get a lot of feedback that people are seeking ease of migration” as they move to a high-k solution.
S.Y. Chiang, senior vice president at TSMC, said the semiconductor industry went through a similar discovery process two decades ago, when early CMOS developers tried to use an N+ poly gate for both the N-channel and P-channel devices.
“When the industry began to do PMOS, companies found an N+ poly gate doesn’t work well,” Chiang said. “It was difficult to lower the Vt, so some people tried to add a counter dopant into the active region of the silicon channel to try to match the Vt. That caused a lot of problems, and made gate control and short channel effects (SCE) much worse.”
With that history in mind, Chiang said the gate-first approach to high-k ran into similar Vt control problems. Efforts to use capping layers improved gate-first performance, but Chiang said a gate-first cap-layer process “gets very, very complicated and difficult to do.”
Asked about the restrictive design rules (RDRs) required for the gate-last method, Chiang said TSMC has been working with the layout teams at its largest customers to adjust to the gate-last high-k flow.
“With the gate-last technology, we do have some restrictions. There is difficulty in planarizing it. However, if the layout team is willing to change to a new layout style, then they can get a layout density that is as good as with the gate-first approach. And it is not that difficult,” he said, adding that “everybody — the process people as well as the layout people — need to adjust the way they do things in order to make the products competitive.”
Chiang said TSMC’s early 28 nm high-k customers are all large companies that are well-equipped to handle layout changes. “We have had face-to-face meetings, and our high-k strategy has been very well accepted. Later, we will offer more help to the layout people at our smaller customers.”
The fact that TSMC was willing to switch to a gate-last approach “says something about the performance advantage of the gate-last approach,” said Dean Freeman semiconductor manufacturing analyst at Gartner Inc. “Gate first gets you a little bit tighter layout, but TSMC must have seen something they didn’t like when they did their shuttle runs,” comparing the gate-first and gate-last wafers.
Thomas Hoffmann, an IMEC (Leuven, Belgium) high-k research manager, raised some of the performance challenges with the gate-first approach at the 2009 International Electron Devices Meeting (IEDM).5 In a follow-up interview, Hoffmann said the gate-first deposition method makes some sense for low-power devices that don’t require the ultimate in performance.
“For low-power companies, such as Renesas and others, gate-first is possibly the best trade-off. They don’t require all the low Vt‘s and high performance, which is harder to do with gate first. But as they proceed beyond 28 nm, companies will need the extra performance advantage that gate last will deliver.”
1. Cap layers can improve the Vt of gate-first gate stacks. (Source: IMEC)However, for performance-oriented companies that require a lower Vt, Hoffmann said “gate last is a must for high-performance applications. IBM obviously must provide high-performance solutions, and I think they need to bring in additional tricks to achieve low Vt‘s with the gate-first approach. Those tricks have a cost in terms of process complexity or yield. At the end of the day, offsets are possible, but perhaps that is why the other companies in the Fishkill Alliance may be getting nervous.”
Although gate last requires careful control of the etching and CMP steps, gate first also has its process control challenges, Hoffmann said. One of the key steps in gate first is deposition of the capping layer either below or on top of the high-k to adjust the Vt. For example, a thin layer — <1 nm — of La2O3 is deposited on the NMOS devices to achieve the appropriate Vt. The lanthanum layer must be removed from the PMOS devices, which requires patterning with resists, careful etching to avoid damage, and other “highly selective” process steps, Hoffmann said. An Al2O3 capping layer on the PMOS devices is employed to control the Vt (Fig. 1).
“You want the benefit of lanthanum for NMOS, but then you have to remove it for the PMOS,” Hoffmann said. “It is not simple at all to remove resist over a material that is very thin to begin with, while avoiding damage to the capping layer. It requires proper control and selectivity.”
Glen Wilk, business unit manager for ALD and epitaxial products at ASM International NV (Almere, Netherlands), said technologists have been debating the performance, complexity and cost issues between gate-first and gate-last deposition for many years. “What I do see coming is that as the technology scales, it is playing more to the strengths of the gate-last approach. There is better ability to set and control the work functions, a better choice of electrodes due to the lower thermal budget. You get the Vt where you want it and get it to stay there.”
As the industry scales, users of the gate-first approach will find it “difficult to control the PMOS characteristics,” Wilk said. Getting the optimum PMOS work function will “get tougher as devices scale, as the thermal budget gets tighter. It will be tougher to make [gate first] work. There will be an industry-wide focus on gate last.”
The benefits of the gate-last approach, in terms of extra strain and overall work function control, make gate last the best option for both high-performance and low-power applications, Wilk said. “Memory companies may have a little more room to play with. They may be able to accept gate first for a while. It really is becoming important not only for the high-performance guys, but also for low standby power, to look at gate last.”
Taking a dual approach is not the way to go, Wilk said. “Foundries want to have one solution, not many solutions,” he argued. “If they use gate last for performance, they will find a way to make gate last work for low standby power. They need one way to manage. If we are going to get to it, let’s get to it. Let’s not keep trying to force an approach that is going against the sweet spot of gate last.”
Hans Stork, CTO at Applied Materials Inc. (Santa Clara, Calif.), said the gate-first approach requires a carefully controlled etch of the capping layers used to control the Vt, while the gate-last method requires expertise at metal deposition and CMP. “Extendibility wise, gate last appears to have the better long-term outlook.”
Stork notes that foundries are paying close attention to Intel’s 32 nm system-on-chip (SoC) process, which uses a 0.95 nm EOT high-k layer for the high-performance and low-power transistors. “Intel’s SoC process extends the gate-last, high-performance process to low-leakage applications and low-voltage operations,” he said. “It is in the sweet spot for cell phone chips.” Customers are watching how the gate-first vs. gate-last alternatives deliver on work function control, cost/productivity, and yields. Large fabless companies such as Qualcomm Inc. (San Diego) that compete in the cell phone space, Stork said, will demand that their foundry suppliers “match Intel’s performance so they can remain competitive.”
At IEDM, Qualcomm technology executives said they are “very comfortable” with the gate-last technology direction endorsed by TSMC last July. In January, Qualcomm said it also will use GlobalFoundries at the 28 nm node. That will set up a head-to-head competition between the Qualcomm cell phone applications processors made at TSMC with a gate-last high-k process, and the gate-first approach used at GlobalFoundries. The 40 nm Qualcomm-designed cell phone CPUs are high-performance chips, running at 1 GHz in the recently introduced Google smartphone, for example, while requiring mobile-appropriate levels of power consumption.
Mark Bohr, director of process architecture at Intel’s Hillsboro, Ore.-based technology and manufacturing group, said the Atom-based products that use the 32 nm SoC process6 may be about a year away, though the exact schedule depends on the product groups (Fig. 2).
2. Intel’s 32 nm NMOS (left) and PMOS transistors have a gate pitch of 112.5 and use a second-generation high-k/metal gate technology.
Asked if the gate-last process results in a larger die size due to more restrictive design rules (RDRs), Bohr said Intel’s RDRs at the 45 nm node have nothing to do with the replacement gate technology, and everything to do with Intel’s desire to stick with non-immersion lithography. “The gridded design was not to enable our high-k/metal gate,” Bohr said, but to support dry lithography.
Zero interface layer
Researchers — including Intel’s Bohr — seem to agree that HfO2 will continue to be used as the base dielectric material for the medium-term future. Rather than switch to new materials with relatively modest increases in the dielectric constant, the industry is better off to improve on hafnium-based dielectrics, though some companies are attempting to tweak the HfO2 with proprietary additives.
Much attention is being paid to reducing the oxide interfacial layer, which, for example, can account for ~5 Å of a ~10 Å EOT gate insulation layer. “Most thinking in the industry now is how to optimize hafnium, rather than start another five-year quest for a new material,” said Paul Kirsch, manager of Sematech’s high-k program. “From a time and effort perspective, let’s improve the effective k, eliminating the SiO2 interface.”7
At IEDM in December, several papers on zero interface layer (ZIL) technology were presented, including a presentation from the IBM-led Fishkill Alliance, which has used the gate-first approach for the 32/28 nm generation.8 An IMEC ZIL paper at IEDM also used a gate-first approach (Fig. 3).
3. An IMEC high-k/metal gate device with no interfacial layer. Indicated thicknesses are in nm. (Source: IMEC)
T.P. Ma, a professor at Yale University, said ZIL is attractive, but most of the scavenging agents require relatively high-temperature steps to remove the interface layer. That lends itself to the gate-first approach, which supports higher temperatures for the gate stack.
Ma said his understanding is that ZIL “requires a high-temperature chemical reaction” to successfully scavenge the SiO2 interface layer. The gate-first approach, for all of its Vt challenges, is designed to withstand high temperatures, Ma said, while the gate-last approach “tries to avoid” high temperature exposure. The IBM and Sematech ZIL results have been “a pleasant surprise” in that the 5 Å EOT layers have shown acceptable leakage characteristics, Ma said.
The early Sematech ZIL work did involve a gate-first deposition method according to Raj Jammy, vice president of materials and emerging technologies at Sematech. “The ZIL approach does not necessarily depend upon high temperatures, but depends on the oxygen scavenging species,” he said, adding that different species have different thermal processing needs in order to be effective (Fig. 4).
4. An interface layer of 5 Å can account for one-half of the EOT. Sematech created a zero interface layer device in 2009. (Source: J. Huang et al., IEEE VLSI Symposium 2009, Sematech)
An IMEC researcher said, “Our approach to reaching a zero interface layer does indeed require a thermal budget. However, there are other ways of growing an interface-free gate-stack. So this in itself is not a reason for selecting one before the other.” He added that it should be possible to “combine the low EOT of the ZIL gate-first gate stack with an improved effective work function using replacement gate.”
There “is more to do” to improve on the dielectric material and to reduce capacitance of the metal electrodes, Bohr said. Asked about the merits of completely removing the interface layer, “My impression is that is not very useful,” partly because ZIL devices do not exhibit the best channel mobility. “If you create the right kind of interface layer, it doesn’t trap a lot of charge.”
Gartner’s Freeman said high-k/metal gate technology will be a critical differentiator between TSMC and GlobalFoundries, starting at the 28 nm node. One possibility is that IBM and GlobalFoundries will do a “very quick about-face” at the 22 nm node, adopting a gate-last technology. Another possibility is that the gate-first approach may prove more capable of removing the interface layer. “Interface control will be absolutely critical at 16 nm,” Freeman said.
1. J. Markoff, “Intel Says Chips Will Run Faster, Using Less Power,” New York Times, Jan. 27, 2007, p. 1.
2. D. Lammers, “Pressure Builds on Gate-First High-k,” Semiconductor.net, Dec. 9, 2009.
3. D. Lammers, “GlobalFoundries Adds Qualcomm, Supports Gate-First Technology at 28 nm Generation,” Semiconductor.net, Jan. 7, 2010.
4. G.H. Ma, et al., “A Novel ‘Hybrid’ High-k/Metal Gate Process for 28 nm High Performance CMOSFETs,” 2009 IEDM, p. 655.
5. T. Hoffmann, “High-k/Metal Gates: Industry Status and Future Direction,” 2009 IEDM Short Course.
6. C.H. Jan et al., “A 32 nm SoC Platform Technology With 2nd Generation High-k/Metal Gate Transistors,” 2009 IEDM, p. 647.
7. J. Huang et al., “Gate First High-k/Metal Gate Stacks With Zero SiOx Interface Achieving EOT=0.59 nm for 16nm Application,” 2009 Symposium on VLSI Technology.
8. T. Ando, et al., “Understanding Mobility Mechanisms in Extremely Scaled HfO2 (EOT 0.42 nm) Using Remote Interfacial Layer Scavenging Technique and Vt-tuning Dipoles With Gate-First Process,” 2009 IEDM, p. 423.