IC Consolidation, Node Scaling and 3D IC
March 3, 2010
A number electronic industry experts were gathered a few weeks ago at Half Moon Bay to discuss the state of microelectronics at Semi’s annual Industry Strategy Symposium or ISS. Attendees heard plenty of good economic news with forecasters predicting two or more good years of strong growth for the semiconductor industry.
As interesting, to PFTLE, was the theme of fab consolidation that permeated the presentations of analysts from Gartner and Int Business Strategies. The economics behind this move is but another driver for 3D IC.
Bob Johnson of Gartner concludes that by 2014, the ability of the industry to stay on the traditional Moore’s Law rate of technology advancement will depend not upon the laws of physics but upon the laws of economics. He predicts that by 2014, 10 companies at most will be operating fabs at the leading edge:
- 1-2 Non Memory IDMs
- 4-5 Memory Companies
- 3 Foundries
Gartner’s estimated development costs by process node for an advanced SoC design are shown below. They conclude that by 2013 a $2 Billion minimum TAM (total accessible market) would be needed to justify using a 32 nm advanced SoC design.
They see the only qualifying markets in 2013 would be:
- Mobile Phone: $11.8B
- PC: $8.1B
- Video Games: $6.8B
- TV: $3.7B
- Set Top Box: $3.4B
Handel Jones of Int Business Strategies Inc also proposed that migration to 32 and then 22 nm will cause consolidation. While the industry is fragmented into hundreds of semiconductor companies at > 130 nm there will be only 10 to 12 companies operating at the 22nm node.
Another interesting comparison by Jones is that of cost per gate shown in the table below where you can see that the cost per gate actually goes up at 22 nm.
Jones projects design costs for various nodes as shown below. He estimates that required revenues for a 22 nm designed product would have to be $583MM .
The role of 3D IC
Last year we discussed the findings of Prof Paul Franzon of NC State [ see “3-D Equals Two Generations of Scaling“, Semi Int April 2009] , who, at DAC 2008 presented the data shown below and uttered the now infamous remark that “3D IC is worth two generations of scaling”
A year later at DATE (Design Automation and Test – Europe) Toshiba presented a design for a 16 core processor which they claimed showed better performance at one higher node in 3D than a lower node in 2D (see below) [ see PFTLE “Nice Date“, 05/09/2009] .
Whether one generation or two, it is clear from all published results so far that 3D allows you to achieve improved performance at a higher node which translates into lower cost if and when 3D reaches the necessary cost points.
For all the latest on 3D IC and advanced packaging stay linked to PFTLE………