GlobalFoundries, TSMC Square Off at DATE – 2010-03-16 10:07:41 CDT | Semiconductor International.
By David Lammers, News Editor — Semiconductor International, March 16, 2010
Representatives from GlobalFoundries Inc. (Sunnyvale, Calif.) and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) said their companies are focused on tighter cooperation with EDA and IP vendors. The comments were part of a panel discussion on the “Impacts of Continuous Scaling” at the Design, Automation and Test in Europe (DATE) conference, held last week in Dresden, Germany.
The discussion came as GlobalFoundries scrambles to put together an EDA and IP infrastructure to match or improve on the established TSMC design services network. Over the past decade, TSMC has built up an extensive library of tested and hardened cores, and its fabless customers have their own proven IP blocks being manufactured at TSMC’s fabs. GlobalFoundries, for its part, is emphasizing that it is well-positioned to develop even closer relations with its design partners than TSMC has achieved, partly because of its base in Silicon Valley, where many of the IP vendors are located. GlobalFoundries also benefits from its inclusion in the Common Platform alliance, and its merger with the former Chartered Semiconductor Manufacturing Ltd. (Singapore), now referred to as GlobalFoundries Singapore.
One source at the DATE conference said that beyond ARM Ltd. (Cambridge, UK) and Denali Software Inc. (Sunnyvale, Calif.), few IP vendors have managed to achieve consistent profitability. If GlobalFoundries can provide a better business environment for these cash-strapped companies, GlobalFoundries could create a truly reusable IP repository that would complement its customers’ IP libraries, he said.
GlobalFoundries seeks to create an IP repository for its customers.
The foundry executives agreed that design and manufacturing costs are increasing sharply, reducing the number of leading-edge manufacturing companies from 22 at the 65 nm node to a likely dozen manufacturers at the 22 nm generation. While fewer companies may have the resources to tackle leading-edge design and manufacturing, the rewards may be richer than ever as smart phones and other systems reach extremely high volumes, they said.
Design starts are shrinking at a faster pace, going from 1012 65 nm system-on-chip (SoC) design starts to 562 at the 45/40 nm generation, 244 32/28 nm tapeouts, and only 156 22 nm design starts, said Subramani Kengeri, vice president of design solutions at GlobalFoundries, quoting predictions from International Business Strategies and Mentor Graphics.
The time it takes to design a leading-edge SoC is now longer than the product life, as debug and verification take longer and as design teams struggle with leakage issues, Kengeri said. The early adopters now tend to start their designs 18-24 months before a process is qualified, he added, requiring much closer collaboration than ever before. “The goal is to have a tapeout ready on the day that we have the process qualified,” he said.
Debug and verification are taking longer, but leakage is the biggest design problem.
Maria Marced, president, TSMC EuropeMaria Marced, president of TSMC Europe, agreed that costs are going up, noting that it costs 4× as much to develop a 32/28 nm process as it did the 130 nm process. The payback at the 22 nm node will come largely from the huge sales of 4G/LTE generation smart phones, she said. Computing, some consumer SoCs, and certain automotive applications also will drive 22 nm volumes.
The big challenge facing the semiconductor industry is not costs or demand, but the extreme downward pressure on average selling prices (ASPs). The antidote is improved cooperation and less duplication among the EDA companies, IP vendors and foundries, Marced said. “We need less wastage of time and money,” she said. “We in the foundry industry have to work with the EDA and IP companies to make sure everything is done most efficiently.”
Yervant Zorian, chief scientist at Virage Logic Corp. (Fremont, Calif.), said the best way to reduce unit costs is to include DFM and DFT technology early on in the design cycle, calling the approach design for profitability. Kengeri agreed, saying, “Litho awareness has to start at the IP level. DFM at the IP cell is a critical piece” to improving yields. Providing a feedback loop in order to maintain silicon-to-SPICE model correlation is also important, Kengeri said.
Jack Harding, CEO of eSilicon Corp. (Sunnyvale, Calif.), argued, “As things get harder, the supply chain is at odds and complexity degrades cohesiveness.” Harding said his company is among the value chain aggregators that can provide the system awareness and domain knowledge required to shepherd designs to a successful completion.
Harding, who sits on the board of chipmaker RF Microdevices, predicted that the chip industry will see revived merger and acquisition activity this year. Few takeovers occurred last year because companies had such low valuations that they remained “frozen” in terms of M&A deals. This year, he predicted, “M&A activity will be unleashed as valuations grow.”
Investors increasingly want companies to have at least $250M-$500M in annual revenues, forcing companies to merge. “In 2009, people failed to pull the trigger — they were paralyzed. This year, there will be a rash of consolidation deals,” Harding predicted.