EETimes.com – TSMC skips 22 nm, rolls 20-nm process

EETimes.com – TSMC skips 22 nm, rolls 20-nm process.

SAN JOSE, Calif. — Seeking to take the technology lead in the silicon foundry business, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is putting a new spin on its strategy: After the 28-nm node, it plans to skip the 22-nm ”full node” and will move directly to the 20-nm ”half node.”

At its technology conference here, the world’s largest silicon foundry also provided details about its 20-nm CMOS process, which will be the company’s main technology platform after the 28-nm node. TSMC will also not offer an 18-nm process.

TSMC’s 20-nm process is a 10-level metal technology based on a planar technology. It will feature a high-k/metal gate scheme, strained silicon and newfangled ”low-resistance” copper ultra-low-k interconnects–or what it calls ”low-r.” For the 20-nm node, it will only offer a high-k/metal-gate scheme for the gate stack–and not a silicon dioxide option.

TSMC (Hsinchu) will continue to use 193-nm immersion lithography at 20-nm, but it will also deploy a double-patterning and source-mask optimization schemes. Unlike its previous processes in recent times–which focused on low power first–TSMC’s initial 20-nm process will be a high-performance technology. Following that process, it will roll out a low-power technology.

With the announcement, TSMC is seeking to gain an edge over its leading-edge rivals, such a GlobalFoundries, Samsung and UMC. Both Samsung and UMC have said little or nothing about their respective 2x-nm nodes.

By going to 20-nm, TSMC is leapfrogging one rival–at least on paper. Recently, GlobalFoundries Inc. said it is starting work on its 22-nm CMOS process, which is due out in the second half of 2012. TSMC is also looking at the second half of 2012.

In comparison, Intel Corp. is expected to be at the 22-nm node by the fourth quarter of 2011. As for which vendor is leading in the foundry race at 2x-nm, it’s unclear until a company ”beats the drum and announces they are in production,” said Dean Freeman, an analyst with Gartner Inc.

Meanwhile, TSMC is taking a different approach with its process nodes. In the past, TSMC marched down a predictable process path, as defined basically by the ITRS roadmap. Then, it would generally offer a ”half-node” process as a means to migrate customers to the next node.

As of late, TSMC generally pushed its customers to the half-node process, possibly as a means to differentiate itself. For example, TSMC rolled out a 32-nm process, but it will move customers over to the 28-nm technology.

At one time, it was widely believed that TSMC would offer a 22-nm node. ”22-nm was an option for customers, but we decided to skip it,” said Shang-yi Chiang, TSMC’s senior vice president of research and development. In an interview, Chiang said that the move to 20-nm creates a better gate density and chip performance to cost ratio than a 22-nm process technology.

At the 2x-nm foundry node, cost and complexity will continue to escalate for customers. In recent times, TSMC has provided process flows, design kits and intellectual property (IP) to help reduce foundry costs. ”Customers must engage with us at a much earlier stage” at 20-nm to reduce costs and complexity, Chiang told EE Times.

An IBM researcher recently warned of “design rule explosion” beyond the 22-nm node during a paper presentation earlier this month at the International Symposium on Physical Design (ISPD). Kevin Nowka, senior manager of VLSI Systems at the IBM Austin Research Lab, described the physical design challenges beyond the 22-nm node, emphasizing that sub-wavelength lithography has made silicon image fidelity a serious challenge.

TSMC’s 20-nm process features 10-level metal layers, although customers may typically use 6-to-8 layers, he said. The company continues to push bulk CMOS silicon at 20-nm, as it will not migrate to silicon-on-insulator (SOI) or other transistor structures such as FinFETs.

Chiang believes that 20-nm could be the last node that TSMC uses a planar structure. Following that node, possibly 14-nm, TSMC may be forced to go to a FinFET or a 3-D structure.

Like its 45-, 40-, 32- and 28-nm processes, TSMC will use 193-nm immersion lithography at 20-nm. At that node, it will likely use one or more forms of double patterning, source-mask optimization and other technologies. Its main lithography vendor is ASML Holding NV.

At that node, TSMC is also evaluating other lithography candidates, namely EUV and maskless. The foundry provider will initially go with 193-nm immersion at 20-nm production, but it may also deploy EUV or maskless in 2013-to-2014, depending on the viability of those technologies, he said.

ASML recently said that TSMC will take delivery of ASML’s extreme ultraviolet (EUV) lithography system. At some point, TSMC will take delivery of a TwinScan NXE:3100 tool from ASML. The NXE:3100 is a ”pre-production” EUV tool, said to have an NA of 0.25.

In addition, TSMC and Mapper Lithography BV recently claimed that Mapper’s multi-beam e-beam tool located on TSMC’s Fab 12 GigaFab is printing features so far unachievable with current immersion lithography. In 2008, TSMC and Mapper concluded an agreement according to which Mapper would ship its first 300-mm multiple-electron-beam maskless lithography platform for process development and device prototyping to TSMC.

At 28-nm, the company is supposed to roll out its first high-k/metal-gate scheme for the gate stack. At that node, it will also offer a silicon dioxide option. So far, TSMC’s high-k technology is progressing, he said.

Meanwhile, at 20-nm, TSMC will deploy its fifth-generation strain engineering technology and its second-generation high-k/metal-gate scheme. For 20-nm, TSMC will only offer a high-k/metal-gate technology. It will not offer a silicon dioxide scheme for the gate stack.

Originally, TSMC was planning to go with a gate-first high-k technology. Now, it will go with gate-last. There are two basic approaches to the next-generation gate stack in logic designs. IBM’s ”fab club” is using a gate-first approach, while Intel is deploying a rival replacement-gate or gate-last technology. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.

”The real key difference in the gate-last approach (is that) we use two different gate metals, one metal for the P channel and one metal for N channel. For the gate-first approach, we use the same metal for N and P channel. In gate-last, we can freely adjust voltage for both N channel and P channel. Gate-first has difficulty doing that. So that’s a major difference,” Chiang said in a recent presentation.

For years, TSMC has deployed low-k dielectrics, based on Applied Materials Inc.’s Black Diamond technology. At 28-nm, TSMC is using a carbon-doped oxide process with a ”k” effective number of 2.6.

At 20-nm, TSMC will use an in-house low-k material. the ”k” effective number will move to 2.3. ”Pushing low-k is very difficult,” due to the porous materials and packaging issues, he said.

So instead of pushing the constant, TSMC is taking another approach: It is moving to ”low-r” instead of low-k. ”We will lower the resistance rather than pushing the capacitance,” he said.

Going is towards lower resistance in the interconnect is ”not surprising,” said Gartner’s Freeman. ”You will also see new barrier seed materials at 20,” he said.

TSMC is currently shipping its 40-nm process. Then, it will move to the 28-nm node.

”The first node we’re going to release for the 28-nanometer will be we call the 28 LP (low-power). This is our poly gate and silicon oxide nitrate version. We will establish production at the end of June this year,” Chiang said in a recent presentation.

”The first high-k metal gate we call 28 HP for the high performance application will be introduce the end of September this year, and followed by three months later December will be the 28 HPL. This is the first high-k metal gate introduction for the low power application,” he said.

TSMC’s high-performance 20-nm process is slated to move into risk production in the third quarter of 2012, with volume production scheduled for the first quarter of 2013. Two quarters after the high-performance technology, TSMC is slated to roll out its low-power process.

  1. No trackbacks yet.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s

%d bloggers like this: