TSMC tips process plans: it’s 20nm CMOS with planar transistors – Practical Chip Design – Blog on EDN – 1690000169
Apr 13 2010 12:07PM | Permalink |Comments (2) |
In a keynote speech at TSMC’s San Jose Technical Symposium this morning, the giant foundry’s senior vice president of R/D Shang-Yi Chiang outlined the company’s process plans beyond 28nm. He said TSMC intends to bypass 22nm altogether, and introduce a 20nm process, with volume shipments likely to begin in the first half of 2013.
It is unclear how much difference doing 20nm instead of 22nm will make. The 2nm is probably well inside the range of process variations on critical dimensions, and other decisions in the design and integration of the process may influence density, speed, and power of the resulting chips far more than the nominal CD. But Chiang said the choice of 20nm was dictated by TSMC’s calculation of the ratio of customer value to cost, balanced by their estimate of what the process design team could realistically accomplish.
At first look the 20nm process will be quite familiar to advanced customers, Chiang suggested. TSMC will continue to use planar MOSFETs in bulk silicon, once again eschewing the move either to finFETs or to SoI. The company also plans to stay with the conventional knobs process designers have used to wring passable performance out of increasingly incapable transistors. TSMC will turn the strain engineering knob one more notch, probably this time all the way to the stop. And it will stay with its high-k/metal-gate, gate-last formula. “Using a gate-last, high-k-last process allows us to use different metals in the gates of the P- and N-channel transistors, in order to match the Fermi levels properly,” Chiang explained. “That allows us to balance the performance of the P and N devices more effectively.”
But beneath the surface there will be profound changes. Chiang said the source-drain junction in the new process will be so shallow that major new steps are necessary to form it, preserve it, and make the transistor useful. To begin with, the ultra-shallow junctions require new millisecond-anneal processing to avoid driving the junction too deep into the silicon. But TSMC found that many of the fast-anneal processing systems available to it would have introduced significant pattern dependencies, limiting the freedom of cell and custom-circuit designers. The process team kept comparing equipment until they found a fast-anneal approach that they believe minimizes the pattern sensitivity.
Another problem induced by the very shallow junction is that it becomes very difficult to form adequate, low-resistance contacts to the source and drain regions. Chiang said that the contacts in the new process would be slot-shaped, quite unlike the conventional plugs that rest on the surface of the source and drain. The process will introduce a new metal layer, which TSMC is calling M0, that will be deposited in the slot in the contact. The resulting structure will be significantly more complex than today’s plugs, but it will reduce contact resistance, and hence transistor forward resistance, significantly; in turn greatly reducing circuit designers’ headaches in using the tiny devices.
The theme of lowering resistance will continue into the interconnect layers. “We keep reducing interconnect C by finding lower- and lower-k intermetal dielectric materials,” Chiang said. “But these materials are getting more and more fragile. It is becoming difficult to package the chips without damaging them. So it is time to turn our attention to the other factor in the time-constant, R.”
Chiang said TSMC researchers were looking at several different aspects of interconnect resistance. The company is reducing the thickness of the seed/barrier layers that line the trench in which the copper lies, increasing the cross-section area of the copper. That of course helps with resistance. But it is also vital, Chiang warned, to improve edge roughness and the quality of the interface between barrier and copper. Irregularities in this area cause electron scattering, right at the location of greatest current densities for high-frequency signals, with a disproportionately bad impact on resistance. Further, TSMC researchers are working on the bulk properties of the copper itself to find crystal structures that have lower intrinsic resistance.
Geometry is also a factor in interconnect resistance, especially at high frequencies. If you force current to make a 90-degree turn, it will crowd into a small portion of the bend, near the scattering-prone corner, and increase resistance even further. “In practice 2D angles aren’t too bad,” Chiang related. “But how you do 3D angles is very important to interconnect performance.”
Naturally at 20nm just making patterns on the wafer will be an unprecedented challenge. As of today, Chiang said, TSMC expects to use 193nm immersion lithography once again for the critical layers at 20nm—simply because 193i is the only technology that certainly will be available when production starts. “We are watching both EUV and multi-beam e-beam direct-write, and if either of them is ready in time for production, we will use it,” Chiang allowed.
In order to get the necessary performance on critical layers with 193nm printing, TSMC will for the first time in production employ a configurable light source and source-mask optimization (SMO) software. “We have been going through many iterations developing our algorithms,” Chiang said. “It is a great advantage to have our own mask shop in-house.”
Many of the techniques TSMC will use at 20nm will place at least some restrictions on cell designers and custom-circuit gurus. Already at 28nm TSMC is using dipole illumination to print the poly mask, restricting poly-mask patterns to be unidirectional in exchange for better control of CDs and line-edge roughness. With the use of SMO such restrictions may become more widespread, and for designer who need to push the envelope, more complex. But TSMC appears to be doing everything possible to limit the new complexities to layers frequented by custom designers, so ordinary practitioners of cell-based physical design will see only familiar devices, cells, models, and rules.
That courtesy may not be possible again. Chiang explained that the 20nm process, with its ultra-shallow junctions and extreme strain engineering, will push the planar MOSFET about as far as it can be pushed. Strain, for instance, is approaching the level where thermal cycling or packaging stresses might threaten the mechanical integrity of the transistor. Yet without such techniques, the tiny transistors at these dimensions simply cannot produce sufficient performance to build useful circuits.
“This is probably the last generation for planar structures,” Chiang said. “The next process may very well introduce finFETs.”
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