PC Magazine’s Forward Thinking by Michael J. Miller
Chip-making technology continues to get more complex, but production of future generations remains on track, according to speakers at Intel’s investor day today. William M. Holt, GM, of the Intel Manufacturing group said that 22nm production is on time, and customers should expect to see it exactly two years after the 32nm chips shipped, earlier this year.
According to Holt, the 22-nm SRAM the company showed last September tested all the kinds of features that need to be manufactured. Holt said chip-making technology is getting more complicated, because it takes twice as many steps to produce a 22nm wafer as it did to make a 90nm wafer. But despite increasing complexity and steps, he said, the company has been able to drive down the amount of time it takes to develop each generation.
And he said the technology pipeline is full, and the company has lots of ideas in research for driving technology to 15nm, 11 nm, and 8 nm nodes, including such things as devices built on “III-V” semiconductors. But he said Intel wasn’t ready to disclose its specific technology on future nodes yet. He said Intel’s vision only extends about 10 years, but sees nothing in the pipeline to suggest that innovation is slowing down.
Holt defended Intel’s choices over the years, such as waiting to develop copper interconnects to 130nm instead of at 180nm; choosing bulk silicon over silion-on-insulator; moving to strained silicon transistors; holding off on immersion lithography until 32nm instead of using it at 45nm; implementing high-k metal gate, which he said Intel has been working on for more than a decade; and choosing the “gate last” process for using high-k metal gate. Picking the right materials took many years, he said, and choosing the right process flow is as important as choosing materials.
He talked about how Intel was able to get great yield from its process, showing a 8-core Xeon wafer that was completely usable. He talked about continuing improvements in denstity and performance, saying Intel has the tightest gate pitch and highest drive current of any 32nm or 28 nm technology yet disclosed, even though it is shipping while others are just talking. He noted that in the transition from 4-core to 6-core Xeon, the company was able to had 50% more cores and 50% more cache in about the same size, moving from 731 million transistors to 1.17B transistors, yielding 1.8 times the number of transistors per mm.
Andy Bryant, Intel’s Chief Administrative Officer, gave a presentation on the advantage Intel has by both designing and manufacturing chips. For instance, he said, in 2008, lots of companies talked about shipping 32nm products, but so far, only Intel is shipping. He said, the difference was high-k metal gate transistors.
His talk centered on how very few companies can now afford to build a leading edge factory (about six today, he said), and the cost of R&D in designing chips is becoming a bigger part of revenue, making it harder for fabless semiconductor companies as well. He talked about how Intel needs to invest in new factories. For instance, he said, if the company had stayed on 65 nm technology, it would need 4 times the number of factories it needs at 32nm to produce the same number of chips.
Bryant also said factories last longer than most people believe, talking about how they can move from doing CPUs to chipsets and eventually embedded processors; as well as being upgraded over time. For instance, he showed how the company’s “Fab 11X” started construction in 1999, and is now being upgraded to 32nm. Although factories have been getting more expensive, he said the depreciation cost per wafer is actually declining per year, and depreciation per unit is declining even faster. While Intel is affected by all of these trends, having both design and manufacturing in the same company makes the company much more efficient, he said.