Archive for the ‘ IMEC ’ Category

IMEC prepares industry for introduction of vertical transistors

IMEC prepares industry for introduction of vertical transistors.

According to industry sources attending the IMEC Technology Forum in Leuven, Belgium, the chip industry is currently preparing for the introduction of vertical transistors. Shang-yi Chiang, senior vice president of research and development at TSMC said that the company has already decided to use a vertical transistor structure at the 14nm node.

“We looked at the basic device physics, and came to a decision that we cannot use a planar structure at the 14nm node. With a vertical transistor we have better control of the channel,” said Chiang. TSMC will move from 28nm to 20nm, and then to the 14nm generation by the middle of this decade.

IMEC has also now opened the additional 1,200m2 of its cleanroom, which adds 50% to the facility that was opened five years ago. The added space was included to accommodate the NXT: 3100 EUV tool expected to be installed at IMEC by the end of 2010.

IMEC’s Thomas Hoffmann, director of the Front End of the Line (FEOL) program, said, “Today we are getting a lot of questions about FinFETs from the fabless companies that participate in our Insite program.” TSMC’s plans, as well as persistent rumors that Intel may adopt vertical transistors at the 22nm node, are driving the preparation efforts, he added.

“One challenge we and our partners have is unraveling how a gate-last technology on FinFETs will work. For companies moving to FinFETs at either the 22 or 16nm nodes, they want to know what the implications for high-k/metal gate if they go to a non-planar structure,” Hoffmann said in an interview at the IMEC facilities in Leuven.

The gate-last approach, first adopted by Intel at the 45nm node and also selected by foundry TSMC for its 28nm high-k process, has several advantages, Hoffmann said. The PMOS threshold voltage appears to be more stable with the gate-last approach, and an additional strain is achieved on the silicon channel in the PMOS transistor when the polysilicon replacement is removed. However, the gate-first camp, which includes GlobalFoundries, IBM, and the other members of the Fishkill Alliance, argue that the gate-first approach delivers a smaller die size than the gate last approach. Several companies which rely on foundries are now conducting shuttle runs to compare the performance and area of the competing approaches to high-k deposition.

“For low-power logic at 28nm, the gate-first approach can definitely meet the technology targets,”

EETimes.com – TSMC tries to rally support for 450-mm wafers

EE Times: Semi News

TSMC tries to rally support for 450-mm wafers

Peter Clarke

EE Times

(05/10/2010 9:40 $ EDT)

LONDON — A transition to manufacturing on table-top sized 450-mm diameter wafers is an important enabler for cost reduction, according to Jack Sun, chief technology officer of Taiwan Semiconductor Manufacturing Co. Ltd., speaking at the International Electronics Forum, held in Dresden, Germany last week.

Unfortunately, despite saying that he expected 450-mm production to begin by the middle of the decade, Sun could shed no light on how the industry was going to fund what some observers have said could be a $20 billion bill.

“I do believe it is going to happen. No single company can afford it. It is an ecosystem issue; equipment makers, device makers, customers, governments all have to pitch in,” Sun said. “Before the [economic] crisis we thought it would happen in 2012,” said Sun. “Now that’s been pushed a couple of years out. We have to pick up the pace.” Unfortunately very few other chip makers — and almost none of the chipmaking equipment vendors — feel much inclined to help. The only companies expressing any interest in 450-mm wafer processing besides TSMC are Intel and Samsung.

Luc van den Hove, president and CEO of IMEC, said that expansion of the clean rooms at the European research institute could be used to aid progress towards 450-mm wafer production. “The expansion could be used for some early experiments but we are not going to set up a full 450-mm production line. I don’t see that happening in the next couple of years.”

Van den Hove stressed that the main reason for expansion was to accept a second preproduction extreme ultraviolet lithography tool. IMEC’s primary interest was in semiconductor process and device research and much of that could be done on 300-mm diameter wafers regardless of the size of wafer used in commercial production.

via EETimes.com – TSMC tries to rally support for 450-mm wafers.

EETimes.com – IMEC forms ‘more-than-CMOS’ alliance with TSMC

EETimes.com – IMEC forms ‘more-than-CMOS’ alliance with TSMC.


EE Times

LONDON — Luc van den Hove, president and chief executive officer of IMEC (Leuven, Belgium), has said the research institute has entered into a partnership with Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) to develop hybrid “more-than-Moore” process technologies and pass them on to the Taiwanese foundry.Although IMEC works with most leading chip makers on the leading-edge of CMOS materials and process development, there is tremendous scope for creating application-driven variants of CMOS at more mature nodes.

Speaking at the International Electronics Forum in Dresden, Germany, van den Hove said IMEC would develop CMORE platforms for specific applications. Hybrid processes could mix logic and memory with thermal, chemical and optical sensors, with bioelectronic interfaces, with photonics, microelectromechanical systems (MEMS) and RF circuits in BiCMOS processes.

While IMEC has created and is expanding a 300-mm pilot wafer fab for leading-edge research, it has an older 200-mm pilot line that is suitable for developing so-called CMORE processes.

“We will develop CMORE platforms for specific applications and have a partnership with for TSMC to take on the processes from there,” van den Hove told attendees at the conference.

Van den Hove said that for a major foundry like TSMC there was a chicken-or-egg problem in that it could not develop specialized processes until it was sure of volume demand and volume demand would not materialize without the existence of the process. IMEC was in a position to break that impasse and to work with customers in low volumes before passing the process over to TSMC as and when higher volumes of chips are needed.

Finding the sweet spot where an application-specific process appeals to a large number of customers, or at least a few customers who foresee high volumes, will be the key. Such areas could include medical electronics, consumer interfaces or instrumentation.

IMEC has appointed Kees den Otter, former president of TSMC Europe BV, to the position of vice president of emerging business, an apparent indication that IMEC intends to drive its CMORE program on a commercial basis.

Technology diversification and implication on design @ IMEC 2007 TAD conference

Questions_panel_workshop_Nov12.pdf (application/pdf 객체).

Holistic PathFinding : Process to Architecture (Qualcomm) @ IMEC 2007 TAD conference

Qualcomm nowak.pdf (application/pdf 객체).

Design for yield (Virage) @ IMEC 2007 TAD conference

WebCite query result.

Leveraging DfY for higher yield and reliability
Leveraging DfY for Time-to-Volume Acceleration
Infrastructure IP may require external support,
automated tools and equipment
Yield optimization loops leveraged at different
product realization steps during design, fabrication,
test and in-field
Collaborative Environment is necessary to achieve
Yield, Reliability and TTV goals

DFM for physical design (Magma) at 2007 IMEC TAD conference

WebCite query result.

• DFM is a design flow issue!
• No single point solution, but a combination of methods
• Delicate trade-off throughout flow:
• Between avoidance and fix steps, and between other objectives
• Keep GDS2 sign-off levels alive in 45nm!
• Cannot afford loops that involve slow analysis
• Standard cells must remain rock-solid building blocks
• Wires layout patterns must be restricted
• 0-order DFM wisdom for synthesis tools:
• Bigger cells = better
• Lower density = better
• Keep it regular and uniform
• Must be 99.99% correct-by-construction
• … because iterative fixing is insecure and slow