Archive for the ‘ UMC ’ Category

UMC, He Jian terminate merger deal

UMC, He Jian terminate merger deal.

Taiwan’s United Microelectronics Corp. (UMC) has terminated its acquisition agreement with Infoshine Technology Ltd., the holding company of Chinese foundry vendor He Jian Technology Suzhou Co. Ltd. SAN JOSE, Calif. – Taiwan’s United Microelectronics Corp. (UMC) has terminated its acquisition agreement with Infoshine Technology Ltd., the holding company of Chinese foundry vendor He Jian Technology Suzhou Co. Ltd.

This was seen as a blow for UMC, which counted on He Jian for access into the China market. Last year, foundry vendor UMC said it would pay $285 million to acquire the 85 percent of Chinese foundry He Jian that it did not already own. UMC already owned 15 percent of He Jian.

Then, UMC’s proposed acquisition of Chinese foundry He Jian was in jeopardy last year, because of Taiwan government regulations, according to a report issued by a trade group. A report by the U.S.-Taiwan Business Council on the Taiwan semiconductor market states that Taipei is standing in the way of the deal because investment regulations stipulate that there can be no more than three Taiwan chip fabs in China, and that all three are spoken for.

The original merger consideration involved a combination of common shares, ADR and cash as options for payment to He Jian’s shareholders. ”However, an investment regulation governing foreign holdings of Taiwanese securities, coupled with other restrictions from the amended operating rules of the Taiwan Stock Exchange Corporation for issuing new shares to merge foreign unlisted companies, precluded the issuance of common shares or ADR as payment options,” according to UMC.

”Meanwhile, He Jian’s shareholders had not decided whether to accept a cash-only merger. As such, based on considerations of timing and changes in the industry environment, the board resolved today to terminate the merger agreement,” according to UMC.

Going forward, UMC said it will continue seeking possible alternatives with He Jian shareholders, including a full or partial acquisition of He Jian in cash upon revaluation.

At a low-key event in Taiwan earlier this year, silicon foundry vendor UMC celebrated its accomplishments during its 30th anniversary. But will 2010 be UMC’s last party? Despite the current upturn and renewed growth at UMC, many wonder if the foundry vendor will survive in the long run, as the company has fallen behind the technology curve.

At one time, the company sat comfortably as the world’s second largest foundry vendor, behind neighbor Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Now, it faces competition from a trio of strong players, including TSMC, GlobalFoundries and Samsung Electronics Co. Ltd.

Going forward, UMC has two choices. The company could continue to go it alone-without a big R&D partner. Or, UMC could get acquired.

Some believe that GlobalFoundries or its big investor–Abu Dhabi’s Advanced Technology Investment Co. (ATIC)–may take a stake in UMC in return for fab capacity. In fact, there was once a rumor that ATIC would buy UMC.

Others believe that TSMC may buy UMC. There have been talks over the years about such a deal taking place.

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EETimes.com – Analysis: Whats next for UMC?

EETimes.com – Analysis: Whats next for UMC?.

SAN JOSE, Calif. — At a low-key event in Taiwan this week, silicon foundry vendor United Microelectronics Corp. (UMC) celebrated its accomplishments during its 30th anniversary.

But will 2010 be UMC’s last party? Despite the current upturn and renewed growth at UMC, many wonder if the foundry vendor will survive in the long run, as the company has fallen behind the technology curve, seen a key customer in Xilinx Inc. defect to its rival and been the subject of takeover rumors.

Now, there is speculation that UMC may join IBM Corp.’s fab club or form a new R&D alliance with Texas Instruments Inc., in an effort to play catch-up–or even survive–in the foundry market. Others believe that GlobalFoundries Inc. or its big investor–Abu Dhabi’s Advanced Technology Investment Co. (ATIC)–may take a stake in UMC in return for fab capacity.

In fact, there was once a rumor that ATIC would buy UMC. Rumors aside, this could be a make-or-break year for UMC. At one time, the company sat comfortably as the world’s second largest foundry vendor, behind neighbor Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC).

But besides TSMC, UMC had little competition to speak of, that is, until recently. Now, it faces competition from a trio of strong players, including TSMC, GlobalFoundries and Samsung Electronics Co. Ltd.

Faced with a new set of rivals, UMC’s current strategy may not be viable in today’s climate. The company is a member of Sematech, but besides that, the foundry vendor is not part of a major R&D alliance and prefers to go it alone in technology.

And at one time, UMC attempted to keep up in the process-technology race with TSMC. Now, UMC is quietly shifting towards more of a ”fast follower’’ strategy. It continues to develop leading-edge processes, but it is a step or two behind the leaders.

The fast-follower strategy could keep UMC relevant for the near term, but the question is will its customers continue to believe in the company? And can it keep up in the process-technology race without partners? After several requests, UMC refused to discuss its strategy for EE Times.

Clearly, though, UMC is on a slippery slope. ”I have talked to some people, who say: ‘UMC has totally lost it,’ ” said G. Dan Hutcheson, chief executive of VLSI Research. ”UMC fell behind technically in terms of process technology.’’

On the other hand, UMC is still a viable player, perhaps by default. ”The fabless guys don’t have a lot of choices (at the high-end). If you don’t have a high-volume (product), it’s sometimes hard to deal with TSMC,’’ he said. ”In some cases, UMC’s yields are better than TSMC.’’

”UMC is still the No. 2 foundry, but they will possibly drop to number three next year,’’ added Dean Freeman, an analyst with Gartner Inc. In market share, UMC could fall behind GlobalFoundries, he said.

A more pressing question is whether UMC can keep up in the technology race. ”It’s going to be tough, because they don’t have a technology R&D partner,’’ Freeman said.

UMC recently rolled out its 45-/40-nm process and has even talked about its 28- and 20-nm developments. In reality, though, UMC ”is not as aggressive in technology’’ as TSMC and others, Freeman said. UMC remains ”six to nine months behind TSMC.’’

Simply put, UMC is down but not out. ”Bottom line: Don’t count them out just yet,’’ said Steven Pelayo, an analyst with HSBC.

UMC’s roots can be traced to the 1970s, when Taiwan started its IC industry. A government-sponsored R&D organization in Taiwan, the Industrial Technology Research Institute (ITRI), was formed in 1973. By acquiring technology from ITRI, UMC became the first chip maker in Taiwan. At the time, it owned a 4-inch wafer fab.

In the early years, UMC developed and made chips for low-tech toys and games. For years, the company was a minor integrated device manufacturer (IDM), but it finally gained some notoriety in the 1990s. In the early 1990s, UMC developed its own x86-based microprocessor.

Intel Corp. put UMC on the map by suing the Taiwan chip maker for patent infringement. Shortly after those events, UMC exited from the x86-based processor market and decided to switch from an IDM to a foundry strategy.

In doing so, it spun off its chip units into independent companies. The most notable spin off was Mediatek Inc., which has become a powerhouse in the consumer and cell-phone chip business today.

UMC’s early days in the foundry business were colorful and tumultuous. In the 1990s, two of the company fabs mysteriously caught on fire and were destroyed. And at the early part of this decade, UMC’s top executives were involved in an alleged scandal over investing in China.

At the time, the Taiwan government forbad the island’s companies from investing in chip fabs in China. UMC was allegedly involved in investing in a foundry startup in China called He Jian Technology Co. Ltd.

But following a move by the Taiwan government to relax its rules in China, UMC (Hsinchu, Taiwan) last year paid $285 million to acquire the 85 percent of He Jian that UMC did not already own. However, that deal is still pending. A recent report by the U.S.-Taiwan Business Council on the Taiwan semiconductor market stated that Taipei is standing in the way of the deal because investment regulations stipulate that there can be no more than three Taiwan chip fabs in China, and that all three are spoken for.

Despite the problems (and itself), UMC turned into a viable foundry vendor. In the early part of the decade, UMC and TSMC were neck-and-neck in terms of sales. And in 2003, UMC beat TSMC to the punch in the 90-nm market.

More recently, however, TSMC skyrocketed and its sales soared. In contrast, UMC plodded along and struggled to ship its 65-nm technology. Amid a slump in its business, Jackson Hu in 2008 suddenly resigned as chairman and CEO of UMC. UMC announced that Stan Hung was elected to the position of chairman. Shih-Wei Sun was named CEO. Hung had served as UMC’s chief financial officer. Sun was UMC’s COO.

For 2009, UMC reported sales of NT$88.6 billion ($2.8 billion), down 4 percent compared with 2008, the company said. UMC posted a net income for the year of NT$3.9 billion ($121.9 billion), compared with a net loss in 2008.

UMC recently announced it would increase its capital expenditures for 2010 to be between $1.2 billion and $1.5 billion to accommodate strong demand from customers at advanced technology nodes. The company said it spent about $551 million on capital expenditures in 2009.

In total, TSMC was in first place in the overall foundry rankings in 2009, as the company’s sales hit $8.997 billion in 2009, down 15.2 percent over 2008, according to Gartner. TSMC’s share fell from 47 percent in 2008 to 44.8 percent in 2009.

UMC was in second place again. The company’s sales hit $2.730 billion in 2009, down 7.7 percent over 2008, according to Gartner. UMC’s share jumped from 13.1 percent in 2008 to 13.6 percent in 2009.

GlobalFoundries emerged and became the No. 4 player in the foundry business in 2009, according to Gartner. GlobalFoundries, the manufacturing spinoff of Advanced Micro Devices Inc., last year also acquired Singapore’s Chartered Semiconductor Manufacturing Pte. Ltd. Chartered was in third place in 2009.

2010 started off bad for UMC, when Xilinx recently said it will use leading foundry TSMC as one of two foundry suppliers for its 28-nm FPGAs, a major strategy shift that has been the subject of industry rumors and analyst speculation for weeks.

Xilinx (San Jose, Calif.) said it is using TSMC and Samsung Electronics Co. Ltd.’s foundry division to make 28-nm parts, which are expected to begin sampling by the end of this year. Xilinx has long used a two foundry strategy at each process node. Samsung first joined Xilinx’ foundry supplier roster at the 40-nm node, supplanting Toshiba.

Xilinx’ shift to TSMC is a bitter pill for rival foundry UMC, which has been a foundry supplier to Xilinx for more than a decade. Some analysts blamed 65-nm yield issues at UMC for a supply glitch that last summer materially impacted Xilinx sales, speculation which UMC later denied.

UMC will continue to manufacture Xilinx parts at 65-nm, 40-nm and other nodes. According to an Xilinx executive, TSMC and Samsung offered Xilinx the best process technology options for high-performance, low-power process technology at 28-nm.

All is not lost for UMC. ”They have lost Xilinx’ initial 28-nm development work, but they still have majority share of 45- and 65-nm (at Xilinx),’’ said HSBC’s Pelayo. ”And by the way, the vast majority of Xilinx wafers are still done at 65-nm. The 28-nm, high-volume production crossover is at least a couple years away — and who knows what will happen until then.’’

UMC still has a plethora of customers despite the loss. ”As a reminder UMC’s strategy is to not compete on the leading-edge with TSMC and GlobalFoundries. Xilinx was the only customer where they were the primary leading-edge supplier,’’ he said. ”We have confirmed (UMC) has in fact gained some share at Mediatek, Qualcomm and Broadcom. Texas Instruments remains a robust customer too.’’

In fact, UMC is seeing huge demand. Like most foundries, UMC’s biggest problem right now is that its capacity is ”very tight,’’ he added. But the loss of Xilinx, coupled with capacity issues, may have prompted UMC to re-think its strategy.

It is planning a private placement of no more than 10 percent of its total shares or about $400 million. UMC did not elaborate. Analysts believe that UMC is gearing up for a new R&D partnership in an effort to play catch-up in the foundry market.

“In general, it sounds like they are positioning for some kind of technology alliance/licensing. The Street may speculate a new relationship with IBM (similar to the IBM tech licenses that SMIC, Chartered/GlobalFoundries and Samsung have),” said Pelayo in a recent report. ”Alternatively, this could be related to a potential stronger relationship with a key customer like Texas Instruments.”

At one time, there were rumors that UMC would join IBM’s ”fab club,” which includes IBM, GlobalFoundries and Samsung. Meanwhile, ATIC was rumored to have approached UMC in January with a view to taking a stake in UMC and securing additional production capacity. The link was denied at the time.

Meanwhile, UMC is speeding up its fab ramp. The company kicked off official operations of the phase-three and phase-four production facilities at its 300-mm Fab 12A at the Southern Taiwan Science Park (STSP).

UMC is also pushing previously-announced 40-nm process. ‘’Currently, UMC has a total of 10 fabs continuously operating around the world, in Hsinchu, Tainan, Japan, and Singapore,’’ said UMC Chairman Hung at the company’s anniversary party this week in a statement.

”Now, we offer the most advanced 40-nm volume production technologies,’’ he said. ”Independent technology development has reached the leading-edge 28-nm using gate-last high-k/metal- gate technology, with current plans to achieve silicon IP pilot capabilities by end of 2010. Early this year, UMC also began working with customers on planning and initial development of advanced 20-nm technology.’’

The company could also be cooking up a deal with GlobalFoundries. That means UMC would tweak or redo its process efforts and follow the same path as IBM’s fab club. Several years ago, UMC had a process technology effort with IBM and Infineon.

That deal was scrapped because UMC and IBM clashed over the directions of the technology. At the time, UMC didn’t need Big Blue’s technology and it could remain independent. Now, the circumstances are much different and UMC’s future could be hanging on the balance.

Now, three vendors–GlobalFoundries, Samsung and TSMC– appear to be engaged in a new capital spending race in an effort to gain share in the foundry race. The trends could be a problem for the other digital foundries, such as SMIC, UMC and others, many of which cannot keep up with the spending race and will likely fall behind the curve.

The question is clear: Who will be left standing when it’s all said and done? TSMC, GlobalFoundries and Samsung will survive, observers said. UMC and SMIC could hit the wall and/or may get acquired, they added

EETimes.com – GlobalFoundries, ASML linked to UMC fund raising

EETimes.com – GlobalFoundries, ASML linked to UMC fund raising.

LONDON — Foundry chip manufacturer United Microelectronics Corp. (Hsinchu, Taiwan) wants to involve a strategic partner in plans to raise capital according to local reports and market watchers have indicated GlobalFoundries Inc. (Sunnyvale, Calif.) as a candidate.Alternatively a consortium based around a mix of GlobalFoundries, a leading customer and leading equipment supplier ASML Holdings NV could provide a way forward for UMC. GlobalFoundries, which has a major fab under construction in New York, is eager to add capacity quickly and tapping into UMC could allow it to achieve that using the leverage of an additional cash injection.

Earlier in May UMC said it was planning a private placement of no more than 10 percent of its total shares or about $400 million. Analysts noted at the time that UMC lags behind TSMC, Samsung and GlobalFoundries in process technology and that UMC might cut a deal with either IBM or GlobalFoundries or a leading customer such as Texas Instruments (see Analyst: UMC seeks R&D partnership).

Now UMC’s board has approved plans for the issue of up to 1.3 billion new shares worth about $400 million, subject to approval by shareholders, according to a Digitimes report.

UMC wants to involve a strategic partner and is open to involvement from any strategic partner through the private placement, the report said, quoting chief financial officer Chi Tung Liu.

Texas Instruments, ASML and GlobalFoundries are among the potential investors for the placement, the report said, referencing the Chinese LanguageEconomic Daily News, which in turn cited unnamed sources.

Advanced Technology Investment Co., the Abu Dhabi owned parent of GlobalFoundries was rumored to have approached UMC in January 2010 with a view to taking a stake in UMC and securing additional production capacity. The link was denied at the time.

EETimes.com – Analyst: UMC seeks R&D partnership

EETimes.com – Analyst: UMC seeks R&D partnership.


EE Times

SAN JOSE, Calif. — Taiwan’s United Microelectronics Corp. (UMC) is accelerating its fab expansion efforts. It is also planning a private placement of no more than 10 percent of its total shares or about $400 million.Foundry vendor UMC did not elaborate. Analysts believe that UMC is gearing up for a new R&D partnership in an effort to play catch-up in the foundry market. UMC trails behind GlobalFoundries, TSMC and Samsung in process technology, it was noted.

“In general, it sounds like they are positioning for some kind of technology alliance/licensing. The Street may speculate a new relationship with IBM (similar to the IBM tech licenses that SMIC, Chartered/Global Foundries and Samsung,” said Steven Pelayo, an analyst with HSBC, in a report. ”Alternatively, this could be related to a potential stronger relationship with a key customer like Texas Instruments.”

At one time, there were rumors that UMC would join IBM Corp.’s ”fab club,” which includes IBM, GlobalFoundries and Samsung.

As reported earlier this year, Xilinx Inc. said it will use leading foundry TSMC as one of two foundry suppliers for its 28-nm FPGAs, a major strategy shift that has been the subject of industry rumors and analyst speculation for weeks.

Xilinx said it is using TSMC and Samsung Electronics Co. Ltd.’s foundry division to make 28-nm parts. Xilinx’ shift to TSMC is a bitter pill for rival foundry UMC, which has been a foundry supplier to Xilinx for more than a decade.

Meanwhile, UMC is speeding up its fab ramp. The company ”will kick off official operations of the phase-three and phase-four production facilities at its 12-inch Fab 12A at the Southern Taiwan Science Park (STSP) on May 20, compared to the original schedule set for the third quarter,” Pelayo said.

Gate First, or Gate Last: Technologists Debate High-k – 2010-03-10 15:41:15 | Semiconductor International

Gate First, or Gate Last: Technologists Debate High-k – 2010-03-10 15:41:15 | Semiconductor International.

David Lammers, News Editor — Semiconductor International, 3/10/2010

As high-k rolls out beyond Intel Corp.1 to both mobile and high-performance applications, the industry now faces a divided landscape.2 Intel and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) — the largest MPU provider and pure-play foundry, respectively — are backing the replacement metal gate (RMG) or gate-last approach. Their competitors — Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.), GlobalFoundries Inc. (Sunnyvale, Calif.), IBM Corp. (Armonk, N.Y.), and other members of the Fishkill Alliance — are using the gate-first approach, at least for the 28 nm node.3 United Microelectronics Corp. (UMC, Hsinchu, Taiwan) said it will use a hybrid approach employing a gate-last method for the more-difficult PMOS transistor.4

High k cover imageNo matter what deposition flow is used, high-k is offering benefits, which is why the stakes are so high for getting it right. Not only does high-k sharply reduce gate leakage, the gate capacitance scales with a thinner equivalent oxide thickness (EOT). Though mobility may be not quite as high as in a chip using a native oxide, cutting the EOT with high-k enables a shorter gate length and improves the drive current.

However, pressure is building on the gate-first approach. Some high-k experts argue that the high-temperature steps following the high-k dielectric and metal gate deposition cause the Vt to shift, affecting PMOS performance in particular. Others, including John Pellerin, director of technology at GlobalFoundries, argue that the gate-first approach requires less-restrictive layout design rules, provides for a smaller die size, and eases IP porting, while meeting the performance needs of customers at the 32/28 nm node.

“We are unequivocally committed” to the gate-first approach at 28 nm, Pellerin said. “The die size and scaling potential are very critical factors. We get a lot of feedback that people are seeking ease of migration” as they move to a high-k solution.

S.Y. Chiang, senior vice president at TSMC, said the semiconductor industry went through a similar discovery process two decades ago, when early CMOS developers tried to use an N+ poly gate for both the N-channel and P-channel devices.

“When the industry began to do PMOS, companies found an N+ poly gate doesn’t work well,” Chiang said. “It was difficult to lower the Vt, so some people tried to add a counter dopant into the active region of the silicon channel to try to match the Vt. That caused a lot of problems, and made gate control and short channel effects (SCE) much worse.”

With that history in mind, Chiang said the gate-first approach to high-k ran into similar Vt control problems. Efforts to use capping layers improved gate-first performance, but Chiang said a gate-first cap-layer process “gets very, very complicated and difficult to do.”

Asked about the restrictive design rules (RDRs) required for the gate-last method, Chiang said TSMC has been working with the layout teams at its largest customers to adjust to the gate-last high-k flow.

“With the gate-last technology, we do have some restrictions. There is difficulty in planarizing it. However, if the layout team is willing to change to a new layout style, then they can get a layout density that is as good as with the gate-first approach. And it is not that difficult,” he said, adding that “everybody — the process people as well as the layout people — need to adjust the way they do things in order to make the products competitive.”

Chiang said TSMC’s early 28 nm high-k customers are all large companies that are well-equipped to handle layout changes. “We have had face-to-face meetings, and our high-k strategy has been very well accepted. Later, we will offer more help to the layout people at our smaller customers.”

The fact that TSMC was willing to switch to a gate-last approach “says something about the performance advantage of the gate-last approach,” said Dean Freeman semiconductor manufacturing analyst at Gartner Inc. “Gate first gets you a little bit tighter layout, but TSMC must have seen something they didn’t like when they did their shuttle runs,” comparing the gate-first and gate-last wafers.

Thomas Hoffmann, an IMEC (Leuven, Belgium) high-k research manager, raised some of the performance challenges with the gate-first approach at the 2009 International Electron Devices Meeting (IEDM).5 In a follow-up interview, Hoffmann said the gate-first deposition method makes some sense for low-power devices that don’t require the ultimate in performance.

“For low-power companies, such as Renesas and others, gate-first is possibly the best trade-off. They don’t require all the low Vt‘s and high performance, which is harder to do with gate first. But as they proceed beyond 28 nm, companies will need the extra performance advantage that gate last will deliver.”

High k fig 11. Cap layers can improve the Vt of gate-first gate stacks. (Source: IMEC)However, for performance-oriented companies that require a lower Vt, Hoffmann said “gate last is a must for high-performance applications. IBM obviously must provide high-performance solutions, and I think they need to bring in additional tricks to achieve low Vt‘s with the gate-first approach. Those tricks have a cost in terms of process complexity or yield. At the end of the day, offsets are possible, but perhaps that is why the other companies in the Fishkill Alliance may be getting nervous.”

Although gate last requires careful control of the etching and CMP steps, gate first also has its process control challenges, Hoffmann said. One of the key steps in gate first is deposition of the capping layer either below or on top of the high-k to adjust the Vt. For example, a thin layer — <1 nm — of La2O3 is deposited on the NMOS devices to achieve the appropriate Vt. The lanthanum layer must be removed from the PMOS devices, which requires patterning with resists, careful etching to avoid damage, and other “highly selective” process steps, Hoffmann said. An Al2O3 capping layer on the PMOS devices is employed to control the Vt (Fig. 1).

“You want the benefit of lanthanum for NMOS, but then you have to remove it for the PMOS,” Hoffmann said. “It is not simple at all to remove resist over a material that is very thin to begin with, while avoiding damage to the capping layer. It requires proper control and selectivity.”

Glen Wilk, business unit manager for ALD and epitaxial products at ASM International NV (Almere, Netherlands), said technologists have been debating the performance, complexity and cost issues between gate-first and gate-last deposition for many years. “What I do see coming is that as the technology scales, it is playing more to the strengths of the gate-last approach. There is better ability to set and control the work functions, a better choice of electrodes due to the lower thermal budget. You get the Vt where you want it and get it to stay there.”

As the industry scales, users of the gate-first approach will find it “difficult to control the PMOS characteristics,” Wilk said. Getting the optimum PMOS work function will “get tougher as devices scale, as the thermal budget gets tighter. It will be tougher to make [gate first] work. There will be an industry-wide focus on gate last.”

The benefits of the gate-last approach, in terms of extra strain and overall work function control, make gate last the best option for both high-performance and low-power applications, Wilk said. “Memory companies may have a little more room to play with. They may be able to accept gate first for a while. It really is becoming important not only for the high-performance guys, but also for low standby power, to look at gate last.”

Taking a dual approach is not the way to go, Wilk said. “Foundries want to have one solution, not many solutions,” he argued. “If they use gate last for performance, they will find a way to make gate last work for low standby power. They need one way to manage. If we are going to get to it, let’s get to it. Let’s not keep trying to force an approach that is going against the sweet spot of gate last.”

Hans Stork, CTO at Applied Materials Inc. (Santa Clara, Calif.), said the gate-first approach requires a carefully controlled etch of the capping layers used to control the Vt, while the gate-last method requires expertise at metal deposition and CMP. “Extendibility wise, gate last appears to have the better long-term outlook.”

Stork notes that foundries are paying close attention to Intel’s 32 nm system-on-chip (SoC) process, which uses a 0.95 nm EOT high-k layer for the high-performance and low-power transistors. “Intel’s SoC process extends the gate-last, high-performance process to low-leakage applications and low-voltage operations,” he said. “It is in the sweet spot for cell phone chips.” Customers are watching how the gate-first vs. gate-last alternatives deliver on work function control, cost/productivity, and yields. Large fabless companies such as Qualcomm Inc. (San Diego) that compete in the cell phone space, Stork said, will demand that their foundry suppliers “match Intel’s performance so they can remain competitive.”

At IEDM, Qualcomm technology executives said they are “very comfortable” with the gate-last technology direction endorsed by TSMC last July. In January, Qualcomm said it also will use GlobalFoundries at the 28 nm node. That will set up a head-to-head competition between the Qualcomm cell phone applications processors made at TSMC with a gate-last high-k process, and the gate-first approach used at GlobalFoundries. The 40 nm Qualcomm-designed cell phone CPUs are high-performance chips, running at 1 GHz in the recently introduced Google smartphone, for example, while requiring mobile-appropriate levels of power consumption.

Mark Bohr, director of process architecture at Intel’s Hillsboro, Ore.-based technology and manufacturing group, said the Atom-based products that use the 32 nm SoC process6 may be about a year away, though the exact schedule depends on the product groups (Fig. 2).

High k 22. Intel’s 32 nm NMOS (left) and PMOS transistors have a gate pitch of 112.5 and use a second-generation high-k/metal gate technology.

Asked if the gate-last process results in a larger die size due to more restrictive design rules (RDRs), Bohr said Intel’s RDRs at the 45 nm node have nothing to do with the replacement gate technology, and everything to do with Intel’s desire to stick with non-immersion lithography. “The gridded design was not to enable our high-k/metal gate,” Bohr said, but to support dry lithography.

Zero interface layer

Researchers — including Intel’s Bohr — seem to agree that HfO2 will continue to be used as the base dielectric material for the medium-term future. Rather than switch to new materials with relatively modest increases in the dielectric constant, the industry is better off to improve on hafnium-based dielectrics, though some companies are attempting to tweak the HfO2 with proprietary additives.

Much attention is being paid to reducing the oxide interfacial layer, which, for example, can account for ~5 Å of a ~10 Å EOT gate insulation layer. “Most thinking in the industry now is how to optimize hafnium, rather than start another five-year quest for a new material,” said Paul Kirsch, manager of Sematech’s high-k program. “From a time and effort perspective, let’s improve the effective k, eliminating the SiO2 interface.”7

At IEDM in December, several papers on zero interface layer (ZIL) technology were presented, including a presentation from the IBM-led Fishkill Alliance, which has used the gate-first approach for the 32/28 nm generation.8 An IMEC ZIL paper at IEDM also used a gate-first approach (Fig. 3).

high k 33. An IMEC high-k/metal gate device with no interfacial layer. Indicated thicknesses are in nm. (Source: IMEC)

T.P. Ma, a professor at Yale University, said ZIL is attractive, but most of the scavenging agents require relatively high-temperature steps to remove the interface layer. That lends itself to the gate-first approach, which supports higher temperatures for the gate stack.

Ma said his understanding is that ZIL “requires a high-temperature chemical reaction” to successfully scavenge the SiO2 interface layer. The gate-first approach, for all of its Vt challenges, is designed to withstand high temperatures, Ma said, while the gate-last approach “tries to avoid” high temperature exposure. The IBM and Sematech ZIL results have been “a pleasant surprise” in that the 5 Å EOT layers have shown acceptable leakage characteristics, Ma said.

The early Sematech ZIL work did involve a gate-first deposition method according to Raj Jammy, vice president of materials and emerging technologies at Sematech. “The ZIL approach does not necessarily depend upon high temperatures, but depends on the oxygen scavenging species,” he said, adding that different species have different thermal processing needs in order to be effective (Fig. 4).

High k 44. An interface layer of 5 Å can account for one-half of the EOT. Sematech created a zero interface layer device in 2009. (Source: J. Huang et al., IEEE VLSI Symposium 2009, Sematech)

An IMEC researcher said, “Our approach to reaching a zero interface layer does indeed require a thermal budget. However, there are other ways of growing an interface-free gate-stack. So this in itself is not a reason for selecting one before the other.” He added that it should be possible to “combine the low EOT of the ZIL gate-first gate stack with an improved effective work function using replacement gate.”

There “is more to do” to improve on the dielectric material and to reduce capacitance of the metal electrodes, Bohr said. Asked about the merits of completely removing the interface layer, “My impression is that is not very useful,” partly because ZIL devices do not exhibit the best channel mobility. “If you create the right kind of interface layer, it doesn’t trap a lot of charge.”

Gartner’s Freeman said high-k/metal gate technology will be a critical differentiator between TSMC and GlobalFoundries, starting at the 28 nm node. One possibility is that IBM and GlobalFoundries will do a “very quick about-face” at the 22 nm node, adopting a gate-last technology. Another possibility is that the gate-first approach may prove more capable of removing the interface layer. “Interface control will be absolutely critical at 16 nm,” Freeman said.

References

1. J. Markoff, “Intel Says Chips Will Run Faster, Using Less Power,” New York Times, Jan. 27, 2007, p. 1.
2. D. Lammers, “Pressure Builds on Gate-First High-k,” Semiconductor.net, Dec. 9, 2009.
3. D. Lammers, “GlobalFoundries Adds Qualcomm, Supports Gate-First Technology at 28 nm Generation,” Semiconductor.net, Jan. 7, 2010.
4. G.H. Ma, et al., “A Novel ‘Hybrid’ High-k/Metal Gate Process for 28 nm High Performance CMOSFETs,” 2009 IEDM, p. 655.
5. T. Hoffmann, “High-k/Metal Gates: Industry Status and Future Direction,” 2009 IEDM Short Course.
6. C.H. Jan et al., “A 32 nm SoC Platform Technology With 2nd Generation High-k/Metal Gate Transistors,” 2009 IEDM, p. 647.
7. J. Huang et al., “Gate First High-k/Metal Gate Stacks With Zero SiOx Interface Achieving EOT=0.59 nm for 16nm Application,” 2009 Symposium on VLSI Technology.
8. T. Ando, et al., “Understanding Mobility Mechanisms in Extremely Scaled HfO2 (EOT 0.42 nm) Using Remote Interfacial Layer Scavenging Technique and Vt-tuning Dipoles With Gate-First Process,” 2009 IEDM, p. 423.

EETimes.com – Report: Abu Dhabi seeks stake in UMC

EETimes.com – Report: Abu Dhabi seeks stake in UMC.

Report: Abu Dhabi seeks stake in UMC
SAN JOSE, Calif. — After buying Singapore’s Chartered Semiconductor Manufacturing Ltd., Abu Dhabi’s Advanced Technology Investment Co. (ATIC) is now looking at buying a stake in Taiwan’s United Microelectronics Corp. (UMC)., according to reports.ATIC has approached UMC for talks on a ”possible stake buy,” according to Reuters. UMC’s stock jumped as a result of the rumors.

ATIC denied the rumors about UMC, the world’s second largest foundry, next to TSMC. ”There’s nothing to it. ATIC’s priority is making sure Globalfoundries, with the integration of Chartered Semiconductor of Singapore, is off to a smooth start, fully backed by ATIC’s focused support,” said Brian Brian Lott, executive director of communications for ATIC, in an e-mail response.

In September, ATIC acquired Chartered for a total of $3.9 billion. Chartered will be folded into GlobalFoundries Inc., the former manufacturing division of Advanced Micro Devices Inc. (AMD).

Pooling resources from Chartered and GlobalFoundries will enable the new company to better compete in the tough wafer supply industry with market leader Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). The combined entity will benefit from GlobalFoundries’ technology expertise while tapping into Chartered’s customer base to boost sales.

With UMC, ATIC believes it can better compete against TSMC, according to the report. Others see a nightmarish integration process between GlobalFoundries, Chartered and UMC.

TSMC purchases US$4.5 billion worth of equipment in 2009

Claire Sung, Taipei; Jessie Shen, DIGITIMES [Tuesday 5 January 2010]

Taiwan Semiconductor Manufacturing Company (TSMC) spent more than NT$145 billion (US$4.57 billion) on machinery equipment in 2009, while rival United Microelectronics Corporation (UMC) allocated around NT$22 billion to equipment, according to respective company filings with the Taiwan Stock Exchange (TSE).

Last year, TSMC distributed around NT$28 billion to Applied Materials and NT$24 billion to ASML, and over NT$10 billion each to Tokyo Electron, Dainippon Screen Manufacturing and KLA-Tencor. These major tool suppliers accounted for almost 70% to the foundry’s total equipment spending for 2009.

TSMC was quoted in previous reports as expecting to begin risk production on 28nm low-power (28LP) node at the end of first-quarter 2010, followed by 28nm high-performance (28HP) between the second and third quarters.

TSMC had reportedly been engaged in ramping yield rates on its 40nm process during the latter half of 2009. The segment accounted for 4% of TSMC’s third-quarter revenues, compared to 1% in the first and second quarters.

Compared to TSMC in expenditures and pace, UMC took a more cautious approach towards capacity expansion last year.

UMC is on track to start pilot production for its 28nm low-power and high-performance nodes in the latter half of 2010, company central R&D vice president SC Chien said in previous reports. Chien noted the majority of UMC’s 2009 capex would be used on R&D for next-generation processes (32nm and beyond),

UMC has claimed it is shipping more 12-inch wafers on 65/55nm and 45/40nm, which took a combined 14% share of UMC’s total revenues in the third quarter of 2009.

TSMC and UMC, respectively, are scheduled to hold their fourth-quarter investors conferences on January 28 and February 3.

via TSMC purchases US$4.5 billion worth of equipment in 2009.