Archive for the ‘ 450mm ’ Category

TSMC to make FinFETs in 450-mm fab

TSMC to make FinFETs in 450-mm fab.

At the SPIE Advanced Lithography conference here, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) outlined more details about its 450-mm fab plans. SAN JOSE, Calif. – At the SPIE Advanced Lithography conference here, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) outlined more details about its 450-mm fab plans.

The silicon foundry giant hopes to process 14-nm FinFET devices in full production on 450-mm wafers by 2015 or 2016, said Shang-Yi Chiang, senior vice president of R&D at TSMC.

As reported, Intel, Samsung and TSMC are pushing hard for 450-mm fabs. Intel has already announced two ”450-mm ready’’ fabs. The fab tool vendors are warming up to 450-mm development, but most are still behind schedule with the technology. Some believe that 450-mm will cause confusion in the supply chain.

Recently, TSMC said it plans to install its first 450-mm line in Taiwan by 2013 to 2014.  It will process wafers at the 20-nm node on 450-mm substrates. Many of the details were not disclosed when TSMC made that initial announcement.

In an interview at SPIE after his keynote, Chiang elaborated on those plans. Initially, TSMC hopes to install a 450-mm pilot line in Fab 12 in Hsinchu, Taiwan. The line will process wafers at the 20-nm node. It hopes to get the pilot line up and running by 2013 to 2014.

Then, TSMC plans to bring up its first 450-mm production fab in Taichung, Taiwan, which will process devices at the 14-nm node. The Taichung plant is called Fab 15.

At 14-nm, TSMC plans to make a switch in transistor structures. At the 20-nm node and above, TSMC will continue to use traditional planar transistors based on bulk CMOS. At 14-nm, the company plans to make the switch from bulk CMOS to FinFET structures, he said.

So, the company will produce 14-nm FinFETs in production in Fab 15. Production is slated for 2015 to 2016.

The TSMC technologist said 450-mm wafers enable a 2.25- to 2.40-fold productivity gain over 300-mm wafers. But he acknowledged there are several challenges with 450-mm, namely to get the equipment vendors on board.

At one time, most fab tool vendors were reluctant to invest in 450-mm. Many believe it is too expensive and there is little or no return-on-investment.

Now, fab tool vendors are warming up to the idea for several reasons. First, Sematech, which is leading the charge in 450-mm, is providing some funding for fab tool vendors in 450-mm. Second, the world’s largest chip makers are pushing hard for 450-mm and fab tool vendors don’t want to lose out on some business.

Chiang in a question and answer session said that ”the government would pay for half of the cost’’ of 450-mm tool R&D, but he did not elaborate.

”We see a bit more willingness on the part of equipment makers’’ to embrace 450-mm, said C.J. Muse, an analyst with Barclays Capital, in a recent report. ”We then think by 2016-2018, we will see adoption of 450-mm.’’

Lam Research Corp. is reportedly beginning to invest in 450-mm. Other fab tool vendors are also quietly developing tools, but 450-mm won’t be cheap.


Drop in the (450-mm) bucket
It could cost about $12 billion in R&D investments for 450-mm, Muse said. ”The move to 300-mm was very much more expensive than the prior wafer transitions. While estimates from VLSI/Sematech suggest the 125-mm transition cost only ~$250-300 million and the 150-mm transition ~$700 million, the 300mm cost ~$12 billion,’’ he said.

”It is assumed that the 450-mm transition will not be cheap, and clearly equipment companies are reluctant to pay the full tab. We will likely see a chicken and egg game, but we do expect chipmakers to help support the tool development efforts with equipment companies, at the same time, sharing some of the higher dollars received in the current golden era of capital intensity,’’ he said.

EETimes.com – TSMC tries to rally support for 450-mm wafers

EE Times: Semi News

TSMC tries to rally support for 450-mm wafers

Peter Clarke

EE Times

(05/10/2010 9:40 $ EDT)

LONDON — A transition to manufacturing on table-top sized 450-mm diameter wafers is an important enabler for cost reduction, according to Jack Sun, chief technology officer of Taiwan Semiconductor Manufacturing Co. Ltd., speaking at the International Electronics Forum, held in Dresden, Germany last week.

Unfortunately, despite saying that he expected 450-mm production to begin by the middle of the decade, Sun could shed no light on how the industry was going to fund what some observers have said could be a $20 billion bill.

“I do believe it is going to happen. No single company can afford it. It is an ecosystem issue; equipment makers, device makers, customers, governments all have to pitch in,” Sun said. “Before the [economic] crisis we thought it would happen in 2012,” said Sun. “Now that’s been pushed a couple of years out. We have to pick up the pace.” Unfortunately very few other chip makers — and almost none of the chipmaking equipment vendors — feel much inclined to help. The only companies expressing any interest in 450-mm wafer processing besides TSMC are Intel and Samsung.

Luc van den Hove, president and CEO of IMEC, said that expansion of the clean rooms at the European research institute could be used to aid progress towards 450-mm wafer production. “The expansion could be used for some early experiments but we are not going to set up a full 450-mm production line. I don’t see that happening in the next couple of years.”

Van den Hove stressed that the main reason for expansion was to accept a second preproduction extreme ultraviolet lithography tool. IMEC’s primary interest was in semiconductor process and device research and much of that could be done on 300-mm diameter wafers regardless of the size of wafer used in commercial production.

via EETimes.com – TSMC tries to rally support for 450-mm wafers.

Group Opposing 450 mm N.Y. Subsidy – 2010-02-08 14:55:52 | Semiconductor International

Group Opposing 450 mm N.Y. Subsidy – 2010-02-08 14:55:52 | Semiconductor International.

A “Concerned Citizen Group” is opposing any New York State funding for a 450 mm wafer development center at CNSE/Sematech in Albany, N.Y. The group told New York politicians that any state funding for 450 mm development would not benefit companies operating in the state, and would be a “reckless waste of taxpayer money.”

David Lammers, News Editor — Semiconductor International, 2/8/2010

An anonymous “Concerned Citizen Group” is claiming that a move is afoot to gain New York State tax dollars to support a 450 mm wafer development effort based in Albany, N.Y. The group has appealed to several New York politicians, arguing that the claimed effort by Sematech and the College of Nanoscale Science and Engineering (CNSE) “is a reckless waste of taxpayer money and should not be pursued.”

The group said a grant request is being prepared for consideration by the New York Legislature that would appropriate tens of millions of dollars for support of a 450 mm development effort. The group said the money would be spent on equipment largely manufactured outside of New York, noting that it will have little benefit on employment in the state.

The group also said that the three companies that are publicly supporting the transition to 450 mm wafers — Intel Corp. (Santa Clara, Calif.), Samsung Electronics Co. Ltd. (Seoul, South Korea) and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) — do not have plans for manufacturing in New York. “None are New York companies and two of the three are from Asia. None have manufacturing facilities in New York nor is there planning to have job facilities in New York.”

The group said any New York State grant to CNSE/Sematech Albany “is of no economic benefit to New York. It is a reckless waste of taxpayer money and should not be pursued.”

Thus far, Sematech’s 450 mm development program has been run by its ISMI subsidiary from a relatively small space in Austin, Texas. The 450 mm program is transitioning to a new phase this year, moving from wafer handling infrastructure to early wafer processing.

450 development timeline (020810-450DevTimeline.jpg)The ISMI 450 mm wafer development effort is moving to a wafer processing stage, starting this year. (Source: ISMI)

Sematech spokeswoman Anne Englander said she was not aware of any discussions by Sematech and CNSE to co-develop a 450 mm development facility. “There is no new news on the 450 mm front,” she said. Steve Janack, a spokesman at Albany NanoTech, said he was “not aware of any discussions with Sematech, or Samsung, Intel or TSMC” regarding 450 mm development.

cnse expansion (020810-Aerial-CNSE.jpg)CNSE has expanded its cleanroom and office space in the past year. (Source: CNSE)

EETimes.com – What’s the impact of 450-mm and EUV delays?

EETimes.com – What’s the impact of 450-mm and EUV delays?.

SAN JOSE, Calif. — Another analyst sees delays for 450-mm fabs and extreme ultraviolet (EUV) lithography–a possible sign that Moore’s Law is in danger of slowing down.

On Thursday (Jan. 21), IC Insights Inc. indicated that there could be delays for two chip-scaling enablers: 450-mm fabs and EUV. Another emerging chip-scaling technology, 3-D devices based on thru-silicon vias (TSVs), remains in the embryonic stages and is ”overhyped,” said Trevor Yancey, an analyst with IC Insights.

Gus Richard, an analyst with Piper Jaffray & Co., also sees delays for 450-mm fabs and EUV. ”We believe that the transition to EUV will (be) challenging at best, unaffordable at the worst and likely significantly delayed,” Richard said in a new report. ”The alternative cost reduction path is larger wafers (450-mm). However, equipment companies are unwilling to fund the R&D for 450-mm development.”

What does that all mean? Perhaps a slowdown in the two-year process technology cycle. ”The underlying economic engine of the semiconductor industry is Moore’s Law and the price elasticity it provides. If the cadence of Moore’s Law slows, we think the growth rate of the semiconductor industry would slow as well,” he warned.

The current recession has delayed the possible transition to the next-generation 450-mm wafer size. 450-mm fabs were supposed to happen in the 2012-to-2014 time frame.

There are some return-on-investment (ROI) issues for fab tool makers. Simply put, the fab tool customer base for 450-mm is too small. The R&D is too costly. ”We estimate that a 450-mm fab in 5-10 years will cost somewhere between $8 billion and $12 billion. In our view, only 2 to 5 companies that will be able to make the transition to a 450-mm due to the high cost,” Richard said.

EUV is also in trouble. On the lithography front, today’s immersion lithography technology is enabling devices down to the 3x-nm node, maybe even the 2x-nm node. Lithography is the crucial technology that drives scaling or Moore’s law, he said.

EUV is supposed to be inserted at the 16-nm logic node in 2013. IC Insights believes EUV will be delayed and may be inserted at the 13-nm node in 2015 or 2016.

”The transition to EUV lithography may take longer and cost more than is expected,” Richard warned. ”NAND and DRAM suppliers will need a production EUV tool by 2012 or 2013 and Intel would like to have EUV by 2014. We estimate that ASML will ship 4 or 5 beta tools in 2010, and it has indicated that these tools will be ready for production in 2012. However, based on our conversations with industry contacts, many believe that EUV will not be ready until 2014 or 2016.”

So what will the industry do instead? ”We believe that the current generation of immersion lithography tools will allow Intel to move to 16-nm and NAND flash suppliers to move to 22-nm, the foundries to move to 28-nm and DRAM manufacturers to move to the 2x-nm nodes,” he said.

”Based on our conversations with lithography experts, double or triple patterning in combination with computational lithography could extend immersion lithography to the 2x-nm node for most manufacturers,” he said. ”We believe that Intel will be able to push immersion lithography to 16nm. However, the extension of immersion to 22-nm and below is likely to add to the cost and complexity of the current immersion lithographic process, potentially making immersion at advanced nodes uneconomical.”

Not all agree, namely ASML Holding NV and Nikon Corp. Both are developing EUV tools.

”ASML is making the bet on EUV; we believe that it is a bold and high stakes bet. We believe that it is too early to predict EUV’s success or failure and more will be known as beta systems are installed in the second half of 2010,” Richard pointed out.