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3-D IC Standardization Begins – Perspectives From the Leading Edge | Blog on Semiconductor International

3-D IC Standardization Begins – Perspectives From the Leading Edge | Blog on Semiconductor International.

3-D IC Standardization Begins

April 15, 2010

Many in the 3-D IC arena have been calling for some standardization over the last few years to help speed things along.       [ see PFTLE “Quotes from the Summit“, 08/09/2009 ] . Standardization is a very important activity for a new technology to become accepted and “usable” in any given infrastructure. We have previously commented on the activity of the 3D Alliance [ see PFTLE, “Recent Activity on 3-D IC Integration”, 07/27/2008 ]

There are many societies and associations involved with standardization activities around the world. One such organization, that we all look to for standards, is JEDEC.  JEDEC is an independent association which facilitates standardization within the solid state technology industry. The mission of JEDEC is to “.. create, publish, and promote the global acceptance of standards, and provide a forum for technical exchange on leading industry topics”. JEDEC standards and publications are “…designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining, with minimum delay, the proper product …”

Any company, organization, or individual conducting business in electronic equipment or electronics-related products is eligible for membership in JEDEC and the JEDEC committees.

JEDEC begins to tackle 3D IC

When I became aware that JEDEC had in fact issued a “document” on 3D IC [ see “3D Interconnect Shaping Future Solutions“, Semi Int, 02/16/2010 ] , I decided to delve further, to make you the reader aware of both the content and the authorship of this document. I stress the point of authorship because, to PFTLE, it is important to know exactly who (company and person ) was involved with preparing the document, especially if it is to become a standard. JEDEC, to their credit, suggests that ” The standards development process should have a balance of interests. Participants from diverse interest categories shall be sought with the objective of achieving balance.” PFTLE believes that we should know exactly who was behind writing all documents – it’s called transparency.

PFTLE was able to make contact with JEDEC and the Chairman of the responsible committee (JC -14.3 see below) but unfortunately the JEDEC position is to not release information about who specifically was involved with drawing up any of their documents (companies or individuals).  PFTLE is aware of at least three of the individuals / companies involved but will respect JEDEC’s position and not reveal them here. PFTLE strongly disagrees with this position because this lack of transparency can only weaken the authority of any  document, standard, rule or regulation.

JEDEC Committees and Publications

JC-14 is responsible for standardizing “quality and reliability methodologies for solid state products”. The committee is comprised of both suppliers and users. Sub committee JC-14.3 handles “Silicon Devices Reliability Qualification and Monitoring”. There are also JEDEC committees on  mechanical package outlines, electrical and thermal characterization, digital logic, RAM memory, memory modules, flash memory and many other topics. 3D IC will certainly require standardization activity in all of these areas and more. In fact PFTLE has heard unsubstantiated rumors that JEDEC is in fact tackling the stacked memory area as we speak.

There are several classifications of documents at JEDEC . JEP 158 is actually a JEDEC “publication” not a JEDEC standard (which would have a “JESD” label).  Documents are defined as  “containing general engineering information on products, procedures, or services, that are not necessarily appropriate for standardization”

So with that long introduction, lets take a look at what is covered here.

This document can be downloaded free of charge from the JEDEC web page:

[ http://www.jedec.org/standards-documents/results/jep-158 ] and I recommend that you do that.

JEP-158 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions

This publication is intended as “..a guideline to describe the extension of standard tests to three-dimensional (3D) chip structures that contain stacks of two or more chips that use through-silicon vias to connect from the front side to the back side of each chip.” The main element of this extension is the addition of appropriate test structures to evaluate the reliability of the TSVs and other new features introduced in the fabrication of 3D products. This publication applies to vias-first process (TSV formation before completion of the silicon device  fabrication), vias-middle (TSV formed in the BEOL or prior to the BEOL process), and a vias-last process (TSV formation after completion of the silicon device fabrication).

Terms and definitions

Good to see that JEDEC has accepted the “vias middle” terminology:

”via-middle: A TSV formed after FEOL processing and prior to or during the BEOL process. NOTE A “via-middle” process is sometimes considered to be part of a “via-first” process.”


Overview of TSV Chip Stack Manufacturing and Reliability

TSV related backside processing

Listed precautions include:

“thinning may adversely affect certain specific transistor designs that need to be addressed at the product level….. Thinning down to 25-50 μm may lead to additional warpage related stress to devices….backside processing may lead to leakage to substrate as well as mobile ion diffusion…Mechanical stresses, which can scale with size, and defects introduced by the far back end of the wafer line and bond and assembly processes, can only be addressed through representative test structure design and processing, followed by stress testing and appropriate electrical and physical characterization”

Reliability Considerations

“Stresses are generated in the Si by the presence of the TSV, due to the differences in CTE between the conductive material of the TSV and that of the Si, and due to the geometry of the TSV……. Some field-effect transistors (FETs) are sensitive to stress, such that the FET electrical characteristics can vary with distance to a nearby TSV…… The connection schemes between the TSVs and chip wiring provide additional opportunities for failure…… the processing needed to fabricate [ the TSV] , the fabrication steps.. thermal excursions can have deleterious effects on small wiring features and on features in low-k dielectrics. Thus an additional set of reliability structures are needed…”

3D TSV Failure Modes

“TSVs can also be a source of a reliability failure……Two types of defects can cause reliability fails in this system. .. if the insulator surrounding the TSV is not continuous or has a defect, it can break down and allow leakage between the TSV conductor and the bulk silicon of the die. …. A second potential TSV problem is a void in the conductive material that makes up a via, or that connects to it. The void can grow over time and cause an open.”

TSV failure concerns………..

“TSVs connect both to other strata and to elements within a stratum. All of these interfaces may be somewhat different from standard packaging or chip fabrication processes and should be tested for reliability. All bonds between strata must be evaluated, especially those located at large distances-to-neutral points (DNP)…. The same interfaces are also vulnerable to electromigration failure, if not properly designed… The integrity of all of these interfaces can be affected by … whether the TSV is fabricated before the rest of the chip (stratum) is built, during the sequence of steps used to build the rest of the chip, or after the chip is built……. Individual test structures should be placed at multiple locations across the chip, and… at varying distances from TSVs”

3-D chip stack TSV test guidelines

Failure modes and detection methods are summarized  in the table shown  below.


Things to be documented and examined in a failure analysis are also discussed.

…the interesting footnote

Before we conclude, lets get back to the authorship issue one more time. An interesting comment that is footnoted on all the pages of this document is “Compliance with this section of the document may require requires U.S. Patent Applications No. 11/351,418 and 11/593,788. Users are advised to assess exposure to patent rights in applying this publication.” Certainly anyone who has looked at 3-D IC from a patent standpoint knows that there is a mine field out there especially due to nomenclature (everyone has had their own nomenclature for 3-D IC through the years). I’ll let you take a look at these specific patent applications yourself, if you choose to. Let me just say that of all the 3-D IC related patents I have personally come across, these were certainly not two of the ones I’d be most concerned about  (NOTE – this is not a legal opinion, just my personal opinion). I then noticed who the patents were assigned to and found that that assigned company was indeed a JEDEC member. Sure would be nice to know whether they had a representative on the 14.3 committee drafting this document…..know what I mean ?

Conclusions on JEDEC JEP-158

PFTLE is very pleased with the content of this JEDEC document. This is a very good read for all those involved with or considering becoming involved with 3-D IC.  It is hoped that JEDEC continues this work and helps develop the necessary standards for  3-D IC. It is also hoped that they reconsider their position on divulging authorship !

For all the latest on 3-D IC and advanced packaging technology stay linked toPFTLE……………………..

EETimes.com – What’s the impact of 450-mm and EUV delays?

EETimes.com – What’s the impact of 450-mm and EUV delays?.

SAN JOSE, Calif. — Another analyst sees delays for 450-mm fabs and extreme ultraviolet (EUV) lithography–a possible sign that Moore’s Law is in danger of slowing down.

On Thursday (Jan. 21), IC Insights Inc. indicated that there could be delays for two chip-scaling enablers: 450-mm fabs and EUV. Another emerging chip-scaling technology, 3-D devices based on thru-silicon vias (TSVs), remains in the embryonic stages and is ”overhyped,” said Trevor Yancey, an analyst with IC Insights.

Gus Richard, an analyst with Piper Jaffray & Co., also sees delays for 450-mm fabs and EUV. ”We believe that the transition to EUV will (be) challenging at best, unaffordable at the worst and likely significantly delayed,” Richard said in a new report. ”The alternative cost reduction path is larger wafers (450-mm). However, equipment companies are unwilling to fund the R&D for 450-mm development.”

What does that all mean? Perhaps a slowdown in the two-year process technology cycle. ”The underlying economic engine of the semiconductor industry is Moore’s Law and the price elasticity it provides. If the cadence of Moore’s Law slows, we think the growth rate of the semiconductor industry would slow as well,” he warned.

The current recession has delayed the possible transition to the next-generation 450-mm wafer size. 450-mm fabs were supposed to happen in the 2012-to-2014 time frame.

There are some return-on-investment (ROI) issues for fab tool makers. Simply put, the fab tool customer base for 450-mm is too small. The R&D is too costly. ”We estimate that a 450-mm fab in 5-10 years will cost somewhere between $8 billion and $12 billion. In our view, only 2 to 5 companies that will be able to make the transition to a 450-mm due to the high cost,” Richard said.

EUV is also in trouble. On the lithography front, today’s immersion lithography technology is enabling devices down to the 3x-nm node, maybe even the 2x-nm node. Lithography is the crucial technology that drives scaling or Moore’s law, he said.

EUV is supposed to be inserted at the 16-nm logic node in 2013. IC Insights believes EUV will be delayed and may be inserted at the 13-nm node in 2015 or 2016.

”The transition to EUV lithography may take longer and cost more than is expected,” Richard warned. ”NAND and DRAM suppliers will need a production EUV tool by 2012 or 2013 and Intel would like to have EUV by 2014. We estimate that ASML will ship 4 or 5 beta tools in 2010, and it has indicated that these tools will be ready for production in 2012. However, based on our conversations with industry contacts, many believe that EUV will not be ready until 2014 or 2016.”

So what will the industry do instead? ”We believe that the current generation of immersion lithography tools will allow Intel to move to 16-nm and NAND flash suppliers to move to 22-nm, the foundries to move to 28-nm and DRAM manufacturers to move to the 2x-nm nodes,” he said.

”Based on our conversations with lithography experts, double or triple patterning in combination with computational lithography could extend immersion lithography to the 2x-nm node for most manufacturers,” he said. ”We believe that Intel will be able to push immersion lithography to 16nm. However, the extension of immersion to 22-nm and below is likely to add to the cost and complexity of the current immersion lithographic process, potentially making immersion at advanced nodes uneconomical.”

Not all agree, namely ASML Holding NV and Nikon Corp. Both are developing EUV tools.

”ASML is making the bet on EUV; we believe that it is a bold and high stakes bet. We believe that it is too early to predict EUV’s success or failure and more will be known as beta systems are installed in the second half of 2010,” Richard pointed out.

Qualcomm’s Nowak: 3-D Faces Cost Issues

Qualcomm Director of Advanced Technology Matt Nowak outlined the cost and technology challenges facing 3-D interconnects in a speech at an IEEE 3-D IC conference. “If this technology adds more than 10% to final costs, it will not be widely used in high-volume wireless technology,” he said.
Phillip Garrou, Contributing Editor — Semiconductor International, 10/6/2009
In a plenary speech at the IEEE 3-D IC conference in San Francisco, Qualcomm Inc. (San Diego) Director of Advanced Technology Matt Nowak said 3-D interconnects face plenty of issues that must be dealt with before the benefits of the approach can be realized.
“While 3-D with TSVs currently has significant industry momentum, more development work is needed to bring this technology to high-volume manufacturing,” Nowak said, adding that TSV (through-silicon via) development and characterization needs to move to leading-edge CMOS, containing strained transistors, ultralow-k dielectrics, and thin die.
Although 300 mm equipment installations are beginning worldwide and test chips are being reported, Nowak noted that a number of issues need to be overcome, including:
• Lack of 300 mm lines in production
• Lack of standard process flows
• Unproven yield/reliability
• Unclear supply chain handoffs
• Lack of consensus on cost targets

The attraction of TSVs is apparent for mobile wireless devices looking for low-cost solutions that improve power efficiency while enhancing performance in terms of bandwidth/milliwatt. Noting that Qualcomm today relies on stacked bare die using wire bond and flip-chip, Nowak said 3-D TSV technology would enable “new architectural solutions that can only be realized with such high-density tier-to-tier connections.”
Many potential 3-D IC users are clamoring for immediate standardization, but Nowak said it may be too early to standardize the technical solutions. Standards eventually will be needed for:
• Nomenclature/definitions
• TSV size, tier thickness, via fill material
• Tier-to-tier pin locations and assignments
• Microbump and passivation materials, properties and geometries
• Reliability test methods
• Metrology

Nowak indicated that foundry TSVs, in which the vias are created in the middle of the process flow, made the most sense and would probably end up being the high-volume manufacturing technology of choice.
Although it is still not resolved where the handoff point will be between the foundry and the outsourced semiconductor assembly and test (OSAT) supplier, Nowak pointed out that handle wafer mounting and dismounting must be done by the same group.
After studying the the cost of ownership models of IMEC, Sematech and EMC-3D, Qualcomm derived its own preliminary economics and determined that the overall cost is dominated by post-fab backside processing. One of the technical conclusions the company reached from its cost modeling is that “thinner is better” — going from 50 µm to 20 µm thick layers could reduce the TSV module portion of the total cost by as much as 25% if the added thin wafer handling costs were not substantial.
Nowak said cost will determine the extent of 3-D IC product adoption. “If this technology adds more than 10% to final costs, it will not be widely used in high-volume wireless technology.”
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