Archive for the ‘ Patterning Technology ’ Category

LithoForum: EUV’s next steps

LithoForum: EUV’s next steps.

LithoForum: EUV’s next steps

Fabtech – http://www.fabtech.org

Obert Wood caption: Obert Wood, head of the EUV program at the Fishkill Alliance, said EUV throughput is a major concernASML is now engaged in “full integration” of the NXE: 3100 EUV scanner expected to begin shipping in the second half of this year, ASML product marketing director Rard de Leeuw said at the Sematech Litho Forum in New York City. Six of the EUV systems, capable of 60 wph throughputs, will be shipped in the second half of this year, kicking off process development activities in preparation for high-volume manufacturing. ASML’s roadmap calls for the high-volume NXT:3300B EUV scanner to begin shipping in the second quarter of 2012.

“The source is now at ASML and is under installation, and five sets of optics have been made by Zeiss with flare now down to 4%. It looks good,” de Leeuw said.
Device makers at the Sematech meeting said they expect to begin using EUV for critical layers in the 2015-2016 time frame.

Bryan Rice, lithography program manager at Sematech’s Albany, N.Y. center, said much of the industry’s anxiety about EUV now centers on its cost effectiveness. “It is difficult to do a cost comparison when the technology is not yet at the required level of maturity. When it is, EUV will be a cost winner,” said Rice, an Intel assignee to Sematech.

Rice cited the improvement in the ability to pump air out of the exposure chamber as one example of EUV’s progress. “Do you know how long it used to take to achieve vacuum? It took nearly a week. Now, ASML can do that in 40 minutes. To me, that rate of progress is very impressive.” De Leeuw said the NXE:3100 remains too large, measuring 10 m long and 3 m wide. “We need to act here, to reduce the footprint” when the high-volume 3300 series scanners begin shipping. “We expect a 40% reduction, to 50 square meters of footprint, with the subfab not larger than the tool.”

ASML is talking to customers now about the NXT:3300 and expects to take its first purchase orders in July. The NXT:3300 will have improved Zeiss optics with a 0.32 NA, and a throughput of 125 wph, largely due to a sharp increase in the source power to 250 W.

EUV can be extended by reducing the 13.4 nm wavelength to 6.8 nm, now an active area of research. “We are studying how to extend EUV, with high NA optics and by cutting the wavelength in half,” de Leeuw said.

Toshikazu Umatate, a vice president at Nikon Precision, said Nikon’s high-volume EUV scanner will be ready in 2014-2015. “We want to match the 16 nm node timing,” Umatate said, adding that Nikon is “coordinating investments with the infrastructure developers.”

Nikon is monitoring the consolidation in the industry, and its likely impact on scanner manufacturers. The five-largest chip companies now spend about 50% of the total industry’s capital investments. While lithography vendors sold roughly a thousand tools in 2000, a decade later the expectation is for shipments of only 200 leading-edge exposure tools in 2010. “It is a higher risk, all-or-nothing situation now,” he said.

De Leeuw also dwelled on ASML’s rising R&D expenditures, saying EUV has cost the Dutch companies $1.5B thus far, with Zeiss spending another $600M. “EUV is here to stay, for many, many years,” he said. However, ASML projects that the semiconductor industry will consume an estimated 167 EUV tools overall. To recoup its investments, the ASML manager said $10B in EUV revenues is needed.

Others also are worried how to recoup their costs. With the track added, an EUV cluster will exceed $100M, said Julie Planchet, a manager at Dow Chemical Co. That unpalatable price tag will require a “new business model” for infrastructure suppliers who will not be able to afford an EUV tool of their own for development purposes.

On the plus side, several speakers at the Litho Forum said the widespread proliferation of mobile and consumer electronics will push semiconductor revenues up, making EUV affordable. Garry Patton, vice president of IBM’s Semiconductor Research and Development Center in East Fishkill, N.Y., said semiconductor revenues were only $1B in 1962, and are now pushing $300B. In the last decade alone, ICs for consumer electronics systems have increased 10X in value. That growth has helped justify the sharp increase in R&D spending, which Patton said has increased 10X in the last decade.

“EUV is the next frontier. Double patterning is too expensive, and by 2015-2016, at the 11 nm node, we will certainly need EUV,” Patton said. Meanwhile, the industry will employ source-mask optimization (SMO) and double patterning, along with design restrictions to ensure litho-friendly patterns. With EUV, Patton said, we can relax some of the constraints on the mask and the light source and avoid the need for double patterning and design restrictions.

“EUV is so important, we need to move full speed ahead,” Patton said, adding that it will be “quite challenging to make it happen by 2015-2016.” Even though immersion lithography was a relatively straightforward addition of water, it took five years for the chip industry to go from the early concept stage to full production in 2008 with “wet” 193 nm scanners. With EUV, there are at least six major changes, including the use of reflective optics and the new wavelength. “There is no pellicle for the EUV masks, and the ability to inspect the mask is one of the key challenges. Getting the source to the right kind of level, and resists, are among the other main challenges,” Patton said.

Sematech CEO Dan Armbrust said rapid progress is needed to reduce the number of defects on the EUV mask blanks, an issue cited by the Litho Forum survey as one of the two key challenges facing EUV lithography (source power was given nearly equal weight in the survey). Sematech is asking the two EUV mask blank suppliers to achieve a 10X reduction in defects, starting with a 2X reduction by July and a further 5X reduction thereafter.

“Two more orders (of defect reduction) are necessary at the supplier locations. If the mask blank defect issue is not solved, all the rest of our efforts will be for naught,” Armbrust said.

Sematech has organized the EUV Mask Inspection (EMI) program for mask blank and patterned mask inspection tools, with seven founding partners committing to a total of $200-300M in funding for the three inspection tools required. Geert Vandenberghe, an IMEC program manager who was called upon to stand in at the Litho Forum for IMEC CEO Luc Van den hove when the volcanic ash forced cancellation of Van den hove’s flight from Belgium to New York, said IMEC has processed a cumulative total of 2,000 wafers on its EUV Advanced Development Tool (ADT) from ASML since June 2008.

“We are on a path toward use of EUV at the 16 nm node, but the No. 1 critical issue has been mask inspection,” Vandenberghe said. He detailed IMEC’s work on EUV resist development, noting that sulfur-containing outgassing remains a concern.
Several device makers took the stage at the Forum, saying they need EUV to relieve the cost pressures presented by double patterning. Jeong-Ho Yeo, a Samsung process development manager, said Samsung “needs to insert double patterning for the 40 nm half-pitch. We hope to go to EUV for 20 nm half-pitch. We want to reduce our costs in three ways: by design rule shrinks, increasing the wafer size, and increasing the throughput of the scanners.”

With double patterning estimated to be 2-3X more expensive than single patterning, Samsung seeks to “either reduce the cost of double patterning or shift to EUV. Low-cost double patterning and high-throughput EUV are crucial in order to stay on the memory roadmap,” Yeo said.

EUV has the potential to be less costly than double patterning. (Source: Samsung Electronics)

Obert Wood, a GlobalFoundries staff member who heads up the EUV development program at the Fishkill Alliance, said 193 nm immersion lithography begins to run out of steam at the 40 nm half pitch. Showing images of contact layers made with both EUV and immersion scanners, Wood said EUV “can resolve spaces of 20 nm between the contact holes with perfect alignment.”

However, Wood cautioned that with Nikon planning to introduce its 0.4 NA high-volume EUV scanner in 2014, “it is slightly alarming that there will be only one supplier for the next few years.” Also, Wood said “mask blank defects are an order of magnitude higher that what is needed for pilot production.”

Turning to the resist development challenge, Wood said line edge roughness (LER) is now 2.5 nm, while “the spec calls for 1.5 nm. We have one resist which currently works for sub-20 nm resolution, but the line width roughness (LWR) is still higher than it needs to be. Pattern collapse is an issue with these thin resists.”

Wood said the “early news is that the quality of the EUV optics from Zeiss is better than expected. Zeiss has done a lot of work on high-refectivity optics, and there is no fundamental reason why we cannot upgrade eventually to 0.7 NA.”

Wood, who played a key role in the early EUV development at Bell Labs in the 1970s and 80s, said device manufacturers are concerned about cost of ownership (CoO) issues. The source power must increase in order to hit the throughput targets outlined by ASML. “Throughput is so important. Unless throughput is more than 100 wph, EUV does not show much cost advantage. My guess is that the early beta tools will not meet the 60 wafers per hour target if the source power goals are not met. And the blank costs are very much an unknown.”

Noting that EUV is clearly too late for the 22 nm node, Wood added that for some chip manufacturers EUV may also miss the 15 nm node. “I think it would be unwise to depend on EUV for the 15 nm generation, though there is some chance the infrastructure will be sufficiently ready in 2013 for early work at that node.”

EETimes.com – Point/Counterpoint: Whats the right path for litho?

EETimes.com – Point/Counterpoint: Whats the right path for litho?.

Back in 1997, Intel led the formation of EUV LLC, a consortium that planned to commercialize extreme ultraviolet lithography by 2005. Advanced Micro Devices, IBM, Infineon and Micron were among the companies that signed on to the effort.

EUV was supposed to have replaced conventional optical lithography by now. But optical lithography is still driving the semiconductor engine, while EUV now is targeted for early production in 2012-or perhaps 2015 or 2016, depending on who’s offering the estimate. Some say it may never work.

Others are pushing for nanoimprint, maskless lithography or an emerging technology called self-assembly. And there are those who hope to extend today’s optical lithography indefinitely.

Was EUV the wrong bet for the industry? If so, what should it be working on instead? And who will benefit in the long run?

During the recent SPIE Advanced Lithography conference and other events, EE Times posed these questions to lithography experts and executives. Here are their responses.

Yan BorodovskyYan Borodovsky Intel Corp. senior fellow and director of advanced lithography at Intel’s Technology and Manufacturing Group

(Though it originally pushed for EUV, Intel is now weighing a mix-and-match lithography strategy.)

“I think complementary lithography is the right direction [for future IC designs]. . . . 193-nm lithography is the most capable and most mature technology that can meet both fidelity and cost-of-ownership requirements, but it has a weakness in terms of resolution. Complementing 193 nm with a new technology might be the best cost-of-ownership, performance and fidelity solution. The complementary technology could be either EUV or e-beam lithography.

“I think introducing EUV as a complementary technology has its challenges for high-volume manufacturing. Introducing multibeam e-beam as a complementary technology [also has its challenges].

“NAND flash makers have a much higher probability of introducing something like EUV before we do. Logic actually has more degrees of freedom in terms of layout, design rules and restrictions. So I can see why Samsung will be more aggressive to deploy EUV. They have no choice but to go to smaller wavelengths, higher NA [numerical apertures] and a K1 of 0.25.”

Dan HutchesonG. Dan Hutcheson CEO of market research firm VLSI Technology Inc.

“I think the industry is going in the right direction. It’s a lot better in this decade than in the last decade. I remember in the 1990s, when everything was on the [next-generation lithography] road map and no one would pull anything off.

“Meanwhile, we have an ongoing business that allocates so many dollars for R&D every year. And if you look out there for future nodes, you need to have two to three alternatives over your existing technology to make sure you can go down Moore’s Law.

“As a last resort, e-beam will always write fine geometries. The downside is that it violates Moore’s Law. Imprint is a very interesting technology; the technology needs to be developed. EUV, too.

“Then we have the existing technology, which is double patterning. But [if I'm a chip maker] I am going to spend a lot of money on [double patterning], because now my litho tool productivity is basically cut in half. So my cost per wafer doubles. And I am going to need twice as many tools, which is great for the equipment industry.”

Burn LinBurn Lin Senior director of the micropatterning division at Taiwan Semiconductor Manufacturing Co. Ltd.

“The industry is betting too much on one horse. I think it’s dangerous to bet on one horse. A lot of people know that.”

Chris MackChris Mack Consultant and “gentleman scientist”

“It’s always risky to bet on one technology that is high risk and not pursue others simultaneously. And I think it’s been a little bit out of whack that we’ve invested too much in trying to make EUV successful and getting too emotionally attached when you say, ‘We’ve got to make sure we’re not distracted by these other technologies, so we’re going to make sure that only EUV is the one we focus on.’ I don’t have a lot of complaints that EUV got a lot of funding. What I’ve got a complaint about is when people try to limit the other options that are the competitors.

“I am an ‘optical forever’ guy. I am a big proponent of doing more [research] on line-edge roughness. I think longer-term research on subassembly is something we should be doing. It was very premature to give up on some of the high-index materials development. If we have stayed the course, I think those high-index materials would have been there to extend double patterning another generation.”

Hans PfeifferHans Pfeiffer Proprietor of HCP Consulting Services

“If you remember, there have been quite a number of alternatives in lithography. One of them was X-ray, a large program that was supposed to extend lithographic capability beyond optical lithography. But optical lithography never fell off the cliff. And that’s the case today. However, I think we’re seeing the cliff a little bit closer now, and that’s what mobilizes all of these additional resources to finally come up with a practical alternative or solution.

“There are sure no winners right now. That’s the reason why many different technologies are being pursued. The top priority is still to further work on 193 nm and extend that to the absolute. This provides some time for EUV, which is the next major contender.

“But are we headed in the wrong direction? There are many different directions being pursued, but none has really so far exceeded EUV. Most large semiconductor companies are pretty much counting on EUV to be there.

“EUV always looked like the impossible dream. But there are tremendous resources behind it. Is EUV late? Yes. Everyone understands that lateness is not only inconvenient, but it’s also expensive.

“Maskless lithography is struggling to regain a certain level of interest in the industry. E-beam had a very successful period and then basically went under. It did not keep up with Moore’s Law.”

Kurt RonseKurt Ronse Director of the lithography department at IMEC

“I think we’re going in the right direction because there are not many alternatives at this moment; [we] either stop scaling or continue to push EUV.

“A lot of progress has been made on EUV. It’s not a done deal; there is a lot of work to be done. [But] in my opinion, the gap between EUV and the alternatives has increased during the last year. All of the other alternatives did not make much progress. They also had difficulties in getting funds. For the alternatives, it will be very challenging to hit their targets. The alternatives have to focus on 16 or 11 nm, because they have some ways to go. If they keep focusing on 32 nm or maybe 22 nm, they will miss their targets.”

Wally RhinesWalden Rhines Chairman and chief executive of Mentor Graphics

“Computational lithography [including OPC and other resolution enhancement techniques] is what will save us from the [soaring costs] of steppers. Computational lithography represents the biggest TAM [total available market] for EDA in the last decade.”

Dan RubinDan Rubin Venture capitalist with Alloy Ventures

“It is increasingly apparent that EUV is not able to leverage the conventional optical lithography infrastructure. The novel innovation required across an unestablished supply chain for EUV sources and reflective masks, and defect inspection continues to require herculean efforts, significant funding and schedule adjustments. If a complete technical solution is assembled in time, the suggested costs will make EUV unaffordable for advanced memory device adoption.

“I [am] a believer in imprint lithography for the memory market. The progress Molecular Imprints has made on less than a $100 million total investment is incredible, and the pace of performance improvements continues unabated. The usability of their CMOS tools and the throughput of their hard drive tools are technically impressive. If they had received a fraction of the dollars and industry attention that have been spent on EUV, they would have sub-32-nm CMOS production tools today.”

Mark Mmelliar-SmithMark Melliar-Smith CEO of nanoimprint lithography vendor Molecular Imprints Inc.

“The industry [has] restricted its vision. It is focusing much, much more on a single solution. I think that’s bad. “If MII had a month’s worth of EUV funding in the past year, we could have moved a long way to solving our remaining issues in the semiconductor market and been ready for production in 12 to 18 months.”

Kazuo UshidaKazuo Ushida President of the Precision Equipment Co. at Nikon Corp.

“For small-volume production, EUV looks very promising. But . . . EUV will be late for the 22-nm half-pitch road map. EUV will appear later, maybe by 16 nm. We have no metrology tools. It will take two years to develop the mask tools.”

EETimes.com – Direct-write litho still facing uphill climb

EETimes.com – Direct-write litho still facing uphill climb.

SAN JOSE, Calif.—Multiple development efforts focused on e-beam direct-write lithography have reported progress this week at the SPIE Advanced Lithography conference. But, at least according to one prominent lithography researcher, production tools are still a minimum of five years away.

Kurt Ronse
IMEC

Based on the length of time it has historically taken for each new lithography technology to move from proof-of-concept to production, e-beam direct-write lithography tools will be available no sooner than 2015, according to Kurt Ronse, lithography department director at nanoelectronics research center IMEC.

Ronse offered some advice to the many companies and consortiums developing e-beam direct write technology: target the 16-nm node, because the technology won’t be commercially viable by the 22-nm node—the target of many of the development efforts.

Ronse also recommended that these groups initially apply their technology to mask-writing tools—where throughput requirement would not be so arduous—as a shorter term, intermediate step.

Chip makers continue to look longingly at direct-write lithography, which could potentially reduce or remove the need for photomasks, which are getting more expensive—according to data presented by Ronse, the cost of a mask set doubles at each new technology node. Analysts and industry executives label the rising cost of masks as the chief culprit behind an ominous trend: declining ASIC starts.

But technical issues—including unacceptably slow wafer writing times—have to date kept e-beam direct write lithography from moving closer to commercial production.

Providing an overview of the latest direct-write development work being done by three European-based companies, Ronse said the resolution of tools is getting closer to acceptable range for the 22- and 16-nm nodes, but that overlay control and throughput remain well short of what is needed.

“It’s a very interesting technology, and I have a lot of respect for the people developing it,” Ronse said. “But in terms of overlay and throughput I think there is a long way to go.”

A number of firms and consortiums that are developing e-beam direct write technologies gave presentations at SPIE, including Mapper Lithography BV, IMS Nanofabrication AG and the eBeam Initiative, a consortium of more than 25 companies headed by Direct2Silicon Inc. Others are also developing e-beam direct-write technologies, including KLA-Tencor Corp., Micronic Laser Systems AB, Vistec Electron Beam Lithography Group and Tokyo Electronic Ltd., in addition to government-backed research and universities.

That there remain so many distinct direct-write development efforts is testament to the technology’s potential market opportunity. Anyone who can bring to production an e-beam direct-write lithography technology stands to cash in, particularly in light of next-generation extreme ultraviolet (EUV) lithography being pushed out further to target production at the 16-nm node. This means lithographers will push 193-nm immersion lithography down to at least 22-nm, but there is widespread consensus that that technology is not extendible to the 11-nm node.

“I don’t want to say that we are desperate, but when the industry is on the cusp of a major change, you are going to see all of these new technologies emerge,” said Franklin Kalk, executive vice president and chief technology officer Toppan Photomasks Inc.

Franklin Kalk
Toppan Photomasks

Toppan (Austin, Texas), a subsidiary of Japan’s Toppan Printing Co. Ltd., is a member of the E-Beam Initiative. Kalk said Toppan recognizes that for some chips that do not sell huge volumes, a full mask set can be cost prohibitive. Toppan supports e-beam direct-write in the hopes that it will eventually enable companies doing lower-volume designs to do critical layers using direct-write while continuing to purchase photomasks for the non-critical layers, which are less expensive but still the majority of a design, Kalk said.

“We see direct-write as keeping open an application space that is going to close,” Kalk said.

At SPIE, the E-Beam Initiative announced the additional of six companies, bringing the total number of members in the consortium to 26. D2S, the managing sponsor of the group, appears to be one of the companies following Ronse’s advice to apply direct-write technology to mask writing. The company announced at SPIE a new design for e-beam mask technology for the production of advanced optical photomasks with circular and curvilinear shapes, which the company said could help extend 193-nm immersion to the 22-nm node.

Another company that is doing as Ronse suggests is IMS (Vienna, Austria). In a keynote presentation at SPIE, Elmar Platzgummer, chief operating officer at IMS, said the company built two proof-of-concept tools last year and is continuing to develop its Projection Mask-Less Lithography (PLM2) technology, with a goal of building systems that offer 256,000 programmable electron multi-beams of 50 keV energy. But IMS is also developing the electron-optical column of a mask exposure tool for writing leading-edge, complex masks. The company’s eMET technology targets the 16-nm node and below.

During a paper presentation Tuesay (Feb. 23), Christof Klein, a project manager at IMS, said the company’s maskless technology should benefit from the knowledge being gained on the mask exposure tool. Klein said IMS is working on the mask exposure tool “very intently.”

Platzgummer said IMS has achieved good results in resolution, but acknowledged that throughput remains too slow. Writing a single 300-mm wafer at 60-nm half pitch still takes 20 hours, he said.

Mapper Lithography (Delft, The Netherlands), meanwhile, is not applying its multiple e-beam technology to mask writing. The company said last week that one of its tools, located at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC)’s Fab 12 in Hsinchu, Taiwan, is printing features so far unachievable with current immersion lithography technology.

In another paper presentation Tuesday, Bert Jan Kampherbeek a co-founder of Mapper and currently the company’s vice president of sales and marketing, said Mapper shipped two “pre-alpha tools” last summer—one to TSMC and one to French technology research organization CEA-Leti.

Kampherbeek said Mapper has shown progress on resolution, including exposure of 20-nm SRAM cells. The company is currently focusing on increasing the throughput of its tools, including adding a moveable stage, Kampherbeek said. Mapper hopes to establish a throughput for its tools of 10 wafers per hour and then cluster 10 tools together in a system that can write 100 wafers per hour.

Mapper’s tools feature 110 electron beams that can be individually switched on and off by means of an optical blanker array.

EETimes.com – SPIE: TSMC jumps on EUV bandwagon

EETimes.com – SPIE: TSMC jumps on EUV bandwagon.

SAN JOSE, Calif. — In a major development, ASML Holding NV said that Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) will take delivery of ASML’s extreme ultraviolet (EUV) lithography system.At some point, possibly next year or sooner, TSMC will take delivery of a TwinScan NXE:3100 tool from ASML. The NXE:3100 is a ”pre-production” EUV tool, said to have an NA of 0.25.

This represents a change in direction for silicon foundry giant TSMC. TSMC has dismissed EUV–at least in the past. For next-generation lithography, the company has been backing maskless lithography. It will continue to do so.

After months of collaboration, foundry chip supplier TSMC and Mapper Lithography BV recently claimed that Mapper’s tool located on TSMC’s Fab 12 GigaFab is printing features so far unachievable with current immersion lithography technology. In 2008, TSMC and Mapper concluded an agreement according to which Mapper would ship its first 300 mm multiple-electron-beam maskless lithography platform for process development and device prototyping to TSMC.

TSMC is also expected to be one the first dedicated foundries conducting on-site EUV development. It will install the new system on its Fab 12 GigaFab for development of future technology nodes.

TSMC is evaluating EUV and other lithography technologies for their potential to optimize cost-effective manufacturing at future technology nodes. EUV technology employs a much shorter wavelength and has the potential to reduce costs associated with current techniques used to stretch 193-nm immersion lithography, making it a promising lithography technology for manufacturing IC’s for future advanced technology nodes.

“TSMC will use a TwinScan NXE:3100 for research and development of future advanced technology nodes,” said Shang-yi Chiang, TSMC’s senior vice president of research and development, in a statement. “EUV is one of next-generation lithography technologies we are investigating.”

Others have also jumped on the EUV bandwagon, including Hynix, Intel, Samsung, Toshiba, among others.

Nano-injection; NGL to make 0.039um2 bitcell for 16nm

  • 나노 인젝션(NanoInjection)이라는 새로운 리소그래피 기술을 이용한다. 이는 가스를 불어 넣는 지점에 전자 빔을 대서 패턴을 그리는방법이다(그림6(b)).
  • 나노 인젝션의 이점은 기존의 전자 빔 리소그래피 기술과는 달리 포토 레지스트가 필요 없다는 점이다. 포토 레지스트를 쓰지 않아도 되기 때문에 리소그래피의 해상도를 높이기 쉽고, 결과적으로 미세한 패턴을 형성할 수 있게 되는 것이다.
  • 하지만 단점도 있다. 기존의 전자 빔 기술 등과 마찬가지로 생산성이 낮다는 것이다. 앞으로 생산성 향상을 위한 연구개발이 진행될 것으로 보인다.
  • Nano injection lithography eliminates the masks of other lithography techniques. Eliminating the masks and the photoresist cuts the patterning process from five steps to one, greatly simplifying production.
  • A new type of lithography, which uses an electron beam to spark a chemical reaction, could provide a cheaper way to build the incredibly tiny transistors that the chipmaking industry will require in a few years.
  • Researchers from Taiwan and the University of California, Berkeley, say they’ve made static random access memory (SRAM) that anticipates 16-nanometer chip features with a new process called nano injection lithography.
  • They say their technique may provide an alternative to lithography that relies on extreme ultraviolet light (EUV), which still is beset by problems and could be extremely expensive.
  • a metallorganic gas, an organic molecule studded with atoms of platinum.
  • An electron beam with a diameter of 4.6 nm is fired at the gas, causing a chemical reaction that deposits the platinum on the silicon chip in the desired pattern, while the rest of the gas flows away.
  • With this hard mask deposited on the silicon, the researchers then use chemicals to etch away exposed silicon and thereby create the desired circuits. The platinum mask is then chemically removed.

EETimes.com – What’s the impact of 450-mm and EUV delays?

EETimes.com – What’s the impact of 450-mm and EUV delays?.

SAN JOSE, Calif. — Another analyst sees delays for 450-mm fabs and extreme ultraviolet (EUV) lithography–a possible sign that Moore’s Law is in danger of slowing down.

On Thursday (Jan. 21), IC Insights Inc. indicated that there could be delays for two chip-scaling enablers: 450-mm fabs and EUV. Another emerging chip-scaling technology, 3-D devices based on thru-silicon vias (TSVs), remains in the embryonic stages and is ”overhyped,” said Trevor Yancey, an analyst with IC Insights.

Gus Richard, an analyst with Piper Jaffray & Co., also sees delays for 450-mm fabs and EUV. ”We believe that the transition to EUV will (be) challenging at best, unaffordable at the worst and likely significantly delayed,” Richard said in a new report. ”The alternative cost reduction path is larger wafers (450-mm). However, equipment companies are unwilling to fund the R&D for 450-mm development.”

What does that all mean? Perhaps a slowdown in the two-year process technology cycle. ”The underlying economic engine of the semiconductor industry is Moore’s Law and the price elasticity it provides. If the cadence of Moore’s Law slows, we think the growth rate of the semiconductor industry would slow as well,” he warned.

The current recession has delayed the possible transition to the next-generation 450-mm wafer size. 450-mm fabs were supposed to happen in the 2012-to-2014 time frame.

There are some return-on-investment (ROI) issues for fab tool makers. Simply put, the fab tool customer base for 450-mm is too small. The R&D is too costly. ”We estimate that a 450-mm fab in 5-10 years will cost somewhere between $8 billion and $12 billion. In our view, only 2 to 5 companies that will be able to make the transition to a 450-mm due to the high cost,” Richard said.

EUV is also in trouble. On the lithography front, today’s immersion lithography technology is enabling devices down to the 3x-nm node, maybe even the 2x-nm node. Lithography is the crucial technology that drives scaling or Moore’s law, he said.

EUV is supposed to be inserted at the 16-nm logic node in 2013. IC Insights believes EUV will be delayed and may be inserted at the 13-nm node in 2015 or 2016.

”The transition to EUV lithography may take longer and cost more than is expected,” Richard warned. ”NAND and DRAM suppliers will need a production EUV tool by 2012 or 2013 and Intel would like to have EUV by 2014. We estimate that ASML will ship 4 or 5 beta tools in 2010, and it has indicated that these tools will be ready for production in 2012. However, based on our conversations with industry contacts, many believe that EUV will not be ready until 2014 or 2016.”

So what will the industry do instead? ”We believe that the current generation of immersion lithography tools will allow Intel to move to 16-nm and NAND flash suppliers to move to 22-nm, the foundries to move to 28-nm and DRAM manufacturers to move to the 2x-nm nodes,” he said.

”Based on our conversations with lithography experts, double or triple patterning in combination with computational lithography could extend immersion lithography to the 2x-nm node for most manufacturers,” he said. ”We believe that Intel will be able to push immersion lithography to 16nm. However, the extension of immersion to 22-nm and below is likely to add to the cost and complexity of the current immersion lithographic process, potentially making immersion at advanced nodes uneconomical.”

Not all agree, namely ASML Holding NV and Nikon Corp. Both are developing EUV tools.

”ASML is making the bet on EUV; we believe that it is a bold and high stakes bet. We believe that it is too early to predict EUV’s success or failure and more will be known as beta systems are installed in the second half of 2010,” Richard pointed out.

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