Archive for the ‘ Process technology ’ Category

Junctionless transistor could simplify chip making, say researchers

Junctionless transistor could simplify chip making, say researchers.

Peter Clarke

2/22/2010 4:48 AM EST

In a move that could revolutionize nanoelectronics manufacturing and the semiconductor industry, scientists at the Tyndall National Institute (Cork, Ireland) have designed and fabricated what they claim is the world’s first junctionless transistor. LONDON — In a move that could revolutionize nanoelectronics manufacturing and the semiconductor industry, scientists at the Tyndall National Institute (Cork, Ireland) have designed and fabricated what they claim is the world’s first junctionless transistor.

The breakthrough is based on the deployment of a control gate around a silicon wire that measures just a few dozen atoms across. The gate can be used to “squeeze” the electron channel to nothing without the use of junctions.

Professor Jean-Pierre Colinge
Tyndall National Institute

The junctionless transistor, otherwise known as the gated resistor, which could simplify manufacturing of transistors at around the 10-nanometer stage, was created a by a team led by Professor Jean-Pierre Colinge (shown left) and a paper on the development has been published in Nature Nanotechnology.

The structure simplifies the production of transistors and also produces a near-ideal sub-threshold slope, extremely low leakage currents and less degradation of mobility with gate voltage and temperature than classical transistors, the researchers have claimed. Nonetheless such device can be made to have CMOS compatibility.

Since their invention transistor- and diode-action has depended on controlling the flow of electrons across junctions giving rise to the familiar NPN and PNP notation for bipolar devices and p- and n-type FETs with sources and drains. Controlling the junction allows the current in the device to be turned on and off and it is the precise fabrication of this junction that determines the characteristics and quality of the transistor and is a major factor in the cost of production. However, as a consequence of the repeated miniaturization predicted by Moore’s Law transistors at the leading edge are becoming so small that conventional transistor architectures are becoming exceedingly difficult to fabricate.

“We have designed and fabricated the world s first junctionless transistor that significantly reduces power consumption and greatly simplifies the fabrication process of silicon chips,” declared Tyndall’s Professor Colinge, in a statement.

Cross section of a silicon wire with wrap-around insulator and overlaid gate

Control gate like a wedding ring
“The current flows in a very thin silicon wire and the flow of current is perfectly controlled by a “wedding ring” structure that electrically squeezes the silicon wire in the same way that you might stop the flow of water in a hose by squeezing it. These structures are easy to fabricate even on a miniature scale which leads to the major breakthrough in potential cost reduction,” explained Professor Colinge.

Professor Colinge’s team used commercial SOI wafers and electron-beam lithography to define silicon nanowires (or nanoribbons) approximately 30 nanometers across and 10-nm thick. After growing a 10-nm gate oxide, the nanowires were uniformly doped by ion implantation, using arsenic to dope the n-type devices and boron fluoride to dope p-type devices.

In the gated resistor, high doping is required to ensure a high current drive and good source and drain contact resistance. The wrap-around gate was formed by the deposition of a 50-nm layer of amorphous silicon. This is doped with an opposing dopant to the channel — so n-type for a p-channel and p-type for an n-channel — and annealed to activate the sites and transform the gate material to polycrystalline silicon.

Professor Colinge and his team also built a junctionless transistor on a silicon nanowire measuring about 10-nm by 10-nm.

Another key challenge for the semiconductor industry is reducing the power consumption of microchips. Minimising current leakage is one of the main challenges in today’s complex transistors. “The Tyndall junctionless devices have near ideal electrical properties and behave like the most perfect transistors. Moreover, they have the potential of operating faster and using less energy than the conventional transistors used in today s microprocessors,” said Professor Colinge.

He went on to say that the junctionless transistor resembles a semiconductor transistor structure, first proposed in 1925 — the so-called Lilienfield device, which was patented in Canada in 1925 by Austro-Hungarian physicist Julius Edgar Lilienfield. But to-date, no-one had been able to fabricate it. Professor Colinge attributed the successful fabrication at Tyndall to the skill and expertise of researchers who were able to fabricate silicon nanowire with a diameter of a few dozen atoms using electron-beam writing techniquesl.

“We are very excited by the outstanding results that Jean-Pierre has achieved,” commented Tyndall CEO, Professor Roger Whatmore. “We are beginning to talk about these results with some of the world’s leading semiconductor companies and are receiving a lot of interest in further development and possible licensing of the technology. These results could not have been achieved without the expertise of Jean-Pierre and his colleagues together with the state-of-the art facilities that we have at Tyndall.”

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IMEC prepares industry for introduction of vertical transistors

IMEC prepares industry for introduction of vertical transistors.

According to industry sources attending the IMEC Technology Forum in Leuven, Belgium, the chip industry is currently preparing for the introduction of vertical transistors. Shang-yi Chiang, senior vice president of research and development at TSMC said that the company has already decided to use a vertical transistor structure at the 14nm node.

“We looked at the basic device physics, and came to a decision that we cannot use a planar structure at the 14nm node. With a vertical transistor we have better control of the channel,” said Chiang. TSMC will move from 28nm to 20nm, and then to the 14nm generation by the middle of this decade.

IMEC has also now opened the additional 1,200m2 of its cleanroom, which adds 50% to the facility that was opened five years ago. The added space was included to accommodate the NXT: 3100 EUV tool expected to be installed at IMEC by the end of 2010.

IMEC’s Thomas Hoffmann, director of the Front End of the Line (FEOL) program, said, “Today we are getting a lot of questions about FinFETs from the fabless companies that participate in our Insite program.” TSMC’s plans, as well as persistent rumors that Intel may adopt vertical transistors at the 22nm node, are driving the preparation efforts, he added.

“One challenge we and our partners have is unraveling how a gate-last technology on FinFETs will work. For companies moving to FinFETs at either the 22 or 16nm nodes, they want to know what the implications for high-k/metal gate if they go to a non-planar structure,” Hoffmann said in an interview at the IMEC facilities in Leuven.

The gate-last approach, first adopted by Intel at the 45nm node and also selected by foundry TSMC for its 28nm high-k process, has several advantages, Hoffmann said. The PMOS threshold voltage appears to be more stable with the gate-last approach, and an additional strain is achieved on the silicon channel in the PMOS transistor when the polysilicon replacement is removed. However, the gate-first camp, which includes GlobalFoundries, IBM, and the other members of the Fishkill Alliance, argue that the gate-first approach delivers a smaller die size than the gate last approach. Several companies which rely on foundries are now conducting shuttle runs to compare the performance and area of the competing approaches to high-k deposition.

“For low-power logic at 28nm, the gate-first approach can definitely meet the technology targets,”

LithoForum: EUV’s next steps

LithoForum: EUV’s next steps.

LithoForum: EUV’s next steps

Fabtech – http://www.fabtech.org

Obert Wood caption: Obert Wood, head of the EUV program at the Fishkill Alliance, said EUV throughput is a major concernASML is now engaged in “full integration” of the NXE: 3100 EUV scanner expected to begin shipping in the second half of this year, ASML product marketing director Rard de Leeuw said at the Sematech Litho Forum in New York City. Six of the EUV systems, capable of 60 wph throughputs, will be shipped in the second half of this year, kicking off process development activities in preparation for high-volume manufacturing. ASML’s roadmap calls for the high-volume NXT:3300B EUV scanner to begin shipping in the second quarter of 2012.

“The source is now at ASML and is under installation, and five sets of optics have been made by Zeiss with flare now down to 4%. It looks good,” de Leeuw said.
Device makers at the Sematech meeting said they expect to begin using EUV for critical layers in the 2015-2016 time frame.

Bryan Rice, lithography program manager at Sematech’s Albany, N.Y. center, said much of the industry’s anxiety about EUV now centers on its cost effectiveness. “It is difficult to do a cost comparison when the technology is not yet at the required level of maturity. When it is, EUV will be a cost winner,” said Rice, an Intel assignee to Sematech.

Rice cited the improvement in the ability to pump air out of the exposure chamber as one example of EUV’s progress. “Do you know how long it used to take to achieve vacuum? It took nearly a week. Now, ASML can do that in 40 minutes. To me, that rate of progress is very impressive.” De Leeuw said the NXE:3100 remains too large, measuring 10 m long and 3 m wide. “We need to act here, to reduce the footprint” when the high-volume 3300 series scanners begin shipping. “We expect a 40% reduction, to 50 square meters of footprint, with the subfab not larger than the tool.”

ASML is talking to customers now about the NXT:3300 and expects to take its first purchase orders in July. The NXT:3300 will have improved Zeiss optics with a 0.32 NA, and a throughput of 125 wph, largely due to a sharp increase in the source power to 250 W.

EUV can be extended by reducing the 13.4 nm wavelength to 6.8 nm, now an active area of research. “We are studying how to extend EUV, with high NA optics and by cutting the wavelength in half,” de Leeuw said.

Toshikazu Umatate, a vice president at Nikon Precision, said Nikon’s high-volume EUV scanner will be ready in 2014-2015. “We want to match the 16 nm node timing,” Umatate said, adding that Nikon is “coordinating investments with the infrastructure developers.”

Nikon is monitoring the consolidation in the industry, and its likely impact on scanner manufacturers. The five-largest chip companies now spend about 50% of the total industry’s capital investments. While lithography vendors sold roughly a thousand tools in 2000, a decade later the expectation is for shipments of only 200 leading-edge exposure tools in 2010. “It is a higher risk, all-or-nothing situation now,” he said.

De Leeuw also dwelled on ASML’s rising R&D expenditures, saying EUV has cost the Dutch companies $1.5B thus far, with Zeiss spending another $600M. “EUV is here to stay, for many, many years,” he said. However, ASML projects that the semiconductor industry will consume an estimated 167 EUV tools overall. To recoup its investments, the ASML manager said $10B in EUV revenues is needed.

Others also are worried how to recoup their costs. With the track added, an EUV cluster will exceed $100M, said Julie Planchet, a manager at Dow Chemical Co. That unpalatable price tag will require a “new business model” for infrastructure suppliers who will not be able to afford an EUV tool of their own for development purposes.

On the plus side, several speakers at the Litho Forum said the widespread proliferation of mobile and consumer electronics will push semiconductor revenues up, making EUV affordable. Garry Patton, vice president of IBM’s Semiconductor Research and Development Center in East Fishkill, N.Y., said semiconductor revenues were only $1B in 1962, and are now pushing $300B. In the last decade alone, ICs for consumer electronics systems have increased 10X in value. That growth has helped justify the sharp increase in R&D spending, which Patton said has increased 10X in the last decade.

“EUV is the next frontier. Double patterning is too expensive, and by 2015-2016, at the 11 nm node, we will certainly need EUV,” Patton said. Meanwhile, the industry will employ source-mask optimization (SMO) and double patterning, along with design restrictions to ensure litho-friendly patterns. With EUV, Patton said, we can relax some of the constraints on the mask and the light source and avoid the need for double patterning and design restrictions.

“EUV is so important, we need to move full speed ahead,” Patton said, adding that it will be “quite challenging to make it happen by 2015-2016.” Even though immersion lithography was a relatively straightforward addition of water, it took five years for the chip industry to go from the early concept stage to full production in 2008 with “wet” 193 nm scanners. With EUV, there are at least six major changes, including the use of reflective optics and the new wavelength. “There is no pellicle for the EUV masks, and the ability to inspect the mask is one of the key challenges. Getting the source to the right kind of level, and resists, are among the other main challenges,” Patton said.

Sematech CEO Dan Armbrust said rapid progress is needed to reduce the number of defects on the EUV mask blanks, an issue cited by the Litho Forum survey as one of the two key challenges facing EUV lithography (source power was given nearly equal weight in the survey). Sematech is asking the two EUV mask blank suppliers to achieve a 10X reduction in defects, starting with a 2X reduction by July and a further 5X reduction thereafter.

“Two more orders (of defect reduction) are necessary at the supplier locations. If the mask blank defect issue is not solved, all the rest of our efforts will be for naught,” Armbrust said.

Sematech has organized the EUV Mask Inspection (EMI) program for mask blank and patterned mask inspection tools, with seven founding partners committing to a total of $200-300M in funding for the three inspection tools required. Geert Vandenberghe, an IMEC program manager who was called upon to stand in at the Litho Forum for IMEC CEO Luc Van den hove when the volcanic ash forced cancellation of Van den hove’s flight from Belgium to New York, said IMEC has processed a cumulative total of 2,000 wafers on its EUV Advanced Development Tool (ADT) from ASML since June 2008.

“We are on a path toward use of EUV at the 16 nm node, but the No. 1 critical issue has been mask inspection,” Vandenberghe said. He detailed IMEC’s work on EUV resist development, noting that sulfur-containing outgassing remains a concern.
Several device makers took the stage at the Forum, saying they need EUV to relieve the cost pressures presented by double patterning. Jeong-Ho Yeo, a Samsung process development manager, said Samsung “needs to insert double patterning for the 40 nm half-pitch. We hope to go to EUV for 20 nm half-pitch. We want to reduce our costs in three ways: by design rule shrinks, increasing the wafer size, and increasing the throughput of the scanners.”

With double patterning estimated to be 2-3X more expensive than single patterning, Samsung seeks to “either reduce the cost of double patterning or shift to EUV. Low-cost double patterning and high-throughput EUV are crucial in order to stay on the memory roadmap,” Yeo said.

EUV has the potential to be less costly than double patterning. (Source: Samsung Electronics)

Obert Wood, a GlobalFoundries staff member who heads up the EUV development program at the Fishkill Alliance, said 193 nm immersion lithography begins to run out of steam at the 40 nm half pitch. Showing images of contact layers made with both EUV and immersion scanners, Wood said EUV “can resolve spaces of 20 nm between the contact holes with perfect alignment.”

However, Wood cautioned that with Nikon planning to introduce its 0.4 NA high-volume EUV scanner in 2014, “it is slightly alarming that there will be only one supplier for the next few years.” Also, Wood said “mask blank defects are an order of magnitude higher that what is needed for pilot production.”

Turning to the resist development challenge, Wood said line edge roughness (LER) is now 2.5 nm, while “the spec calls for 1.5 nm. We have one resist which currently works for sub-20 nm resolution, but the line width roughness (LWR) is still higher than it needs to be. Pattern collapse is an issue with these thin resists.”

Wood said the “early news is that the quality of the EUV optics from Zeiss is better than expected. Zeiss has done a lot of work on high-refectivity optics, and there is no fundamental reason why we cannot upgrade eventually to 0.7 NA.”

Wood, who played a key role in the early EUV development at Bell Labs in the 1970s and 80s, said device manufacturers are concerned about cost of ownership (CoO) issues. The source power must increase in order to hit the throughput targets outlined by ASML. “Throughput is so important. Unless throughput is more than 100 wph, EUV does not show much cost advantage. My guess is that the early beta tools will not meet the 60 wafers per hour target if the source power goals are not met. And the blank costs are very much an unknown.”

Noting that EUV is clearly too late for the 22 nm node, Wood added that for some chip manufacturers EUV may also miss the 15 nm node. “I think it would be unwise to depend on EUV for the 15 nm generation, though there is some chance the infrastructure will be sufficiently ready in 2013 for early work at that node.”

The Impact of Lithography Challenges

http://www.edn.com/professormemory/blog/1640000764/post/1970053597.html

I recently had the opportunity to talk to Dr. Nick Tredennick, and he shared some of the topics that he had included in his recent presentation titled The Last Convergence. His presentation defines three phases in the convergence of semiconductor-related technologies, with the first phase driven by companies like Digital that built modules from discrete components. During the second, integrated circuits began to aggregate discrete components; that expanded performance capability paved the way for minicomputers to displace mainframes. Dr. Tredennick concludes that the subsequent progress in semiconductor cost/performance characteristics brought about the high volume and broad acceptance of personal computer that even pushed minicomputers and workstations into a separate niche. He also observed that “…all of these transitions were in the second dimension; that is, planar components in planar assemblies. In addition, cost-performance drove the design of high-volume systems.”
Dr. Tredennick concludes that wafer stacking is the next convergence; this is a “…compelling change that will create seismic events throughout the semiconductor business.. He views that there are two elements contributing to this convergence. The first is that the shift of personal computers to a more mobile platform also shifted design objectives from a direct cost-performance relation toward the current emphasis on cost-performance/watt ratio. Changing to this new performance target will drive the further integration of chips into 3D devices due to the increased flexibility and functionality of 3D packages.
The second element is more revolutionary and is triggered by the anticipated transition to new light sources as the industry moves toward smaller circuit geometries.
The industry has assumed that the historic improvements in semiconductor performance would continue to follow the time-table of Moore’s Law–even though the investments necessary to achieve smaller transistors has risen exponentially for each new generation,
There is broad agreement today that the anticipated increases in performance, the increasing demand for higher wafer volume, and the expertise to continue the traditional decline in costs will all become more difficult as manufacturing processes march toward sub-20nm line widths. We may have in fact already reached the point that it will not be possible to make the next shrink in lithography on schedule due to the expenses and unresolved technical barriers ahead.
As companies continue to compete for cost/performance advantages while continuing to work on these manufacturing challenges, other alternatives to increasing performance will therefore have to be pursued. Dr. Tredennick expects that these competing OEM and semiconductor companies will likely find that wafer and die packaging techniques will yield better cost and performance results and at lower R&D costs than can be achieved by relying exclusively on the shrinking of transistor sizes.
There is no doubt that we will eventually get to smaller transistors through the use of new illumination sources and other process improvements. However, the time gap between today’s leading edge processes and the future deployment of new light sources will create the opportunity for R&D investment in other cost/performance alternatives. Furthermore by the time most manufacturers have completed that transition, the industry will have been fundamentally transformed in the interim by the convergence to these new stacked-packaging concepts.
The impact of that manufacturing scenario will challenge one of the basic assumptions upon which the semiconductor industry has relied. While value transistors once came from trailing-edge processes for which the plant, equipment, and development costs had been fully

amortized, this changes as progress slows in process lithography, and the most efficient source of the value transistors will migrate to the leading edge of fab facilities as production processes mature. As the reduction in the minimum lithography slows to less than the historic rate, the cost of wafer processing will become more influenced by the operating cost. Once the efficiencies of high volume manufacturing begin to take hold, fabs that have made this transition to the leading–edge processes will also be positioned to make value transistors.
“If the cost of silicon falls toward zero and progress in shrinking transistors slows, then where do system designers turn” for more performance and to add their own value. Dr. Tredennick concludes that the answer to this question will also be found in die and wafer stacking technologies.
The full impact of this scenario is far beyond the scope of this blog. Our worms-eye view of the universe is limited to memory technologies and we can only ask in the next blog what impact this broad trend might have to do with new memory technologies?

 

After first apologizing to Dr. Tredennick if I have somewhat mangled the points of his presentation—I completely agree with Dr. Tredennick assessment of the manufacturing challenges ahead.   
I also believe that this manufacturing issue has a double-barreled impact on the production costs of memory technologies. 
The first impact is relative to the ability to attain the smallest lithography sizes.  Some of the memory companies are already preparing for high-volume production of 25 to 30nm wafers over the next 12 to 18 months and appear to be ahead of the high-volume, production-level processes for logic products.  The memory companies will therefore likely be the first to test these limits.  Whatever additional costs these complexities contribute to the cost/performance ratio, that issue will likely apply equally to both the new memory technologies as well as to the older DRAM/NAND technologies.
However, I suspect there is a second impact to memory products that will not be borne equally by both the new and old memory technologies.  The issue relative to NAND/DRAM is that they are charge storage technologies as opposed to the data storage structures almost universally supported by the new memory technologies.  As lithography measurements below 20nm begin to significantly reduce the mass available by which stored charge technologies can maintain a consistent and predictable level of energy, both the performance and endurance of the cells changes.  This issue has not been shown to apply to the resistance and state-change memory cells.
Clever engineers have always found ways to extend the life of any technology or process, but at some point they can only do so by altering the slope in the decline of the traditional cost-per-bit or cost-per-functionality of the IC. 
I foresee the need to add more error correction or some other form of physical compensation for the existing high-volume memory technologies that will noticeably slow the decline in cost-per-bit of NAND and DRAM.  And as the result of those additional costs, the decline in the cost-per-bit of charge storage memory technologies will be on a less favorable slope than that of most of the new and emerging memory technologies.
We have already suggested one scenario by which new memory technologies can gain a foothold—we’ve presented Dr. Makimoto’s Wave as a possible harbinger of a broad shift in target applications and noted that Intel already appears to be moving in a like manner.  When you change the target application away from the monolithic desktop PC architectures, you also change the value proposition of the technologies. 
Here we have now added Dr. Tredennick’s notice of a second potentially major tremor that will likewise shake the previous foundation of traditional memory cost-per-bit expectations.

EETimes.com – IBM warns of ‘design rule explosion’ beyond 22-nm

EETimes.com – IBM warns of ‘design rule explosion’ beyond 22-nm.

PORTLAND, Ore.—An IBM researcher warned of “design rule explosion” beyond the 22-nanometer node during a paper presentation earlier this month at the International Symposium on Physical Design (ISPD).Kevin Nowka, senior manager of VLSI Systems at the IBM Austin Research Lab, described the physical design challenges beyond the 22-nm node, emphasizing that sub-wavelength lithography has made silicon image fidelity a serious challenge.

“Simple technology abstractions that have worked for many generations like rectangular shapes, Boolean design rules, and constant parameters will not suffice to enable us to push designs to the ultimate levels of performance,” Nowka said.

Solving “design rule explosion,” according to Nowka, involves balancing area against image fidelity by considering the physical design needs at appropriate levels of abstraction, such as within cells. Nowka gave examples of how restricted design rules could reap a three-fold improvement in variability with a small area penalty.

Nowka envisions physical design rules beyond the 22-nm node that are more technology-aware and which make use of pre-analysis and library optimization for improved density and robustness, he said.

IBM described a solution to “design rule explosion” at the 22 nanometer node illustrated in an SRAM chip design.

Also at ISPD, which was held March 14 to 17 in San Francisco, Mentor Graphics Corp. proposed that hardware/software co-design be used for chips, their packages and their printed circuit (pc) boards. A Mentor executive offered an example in which a 26 percent cost savings was realized by performing such a co-optimization of all three systems simultaneously.

“Thinking outside of the chip,” was the key, according to John Park, business development manager for Mentor’s System Design division. By optimizing the interconnect complexity among all three levels of a design–chip, package and pc board—Park claimed that pin counts, packaging costs and high speed I/O can be optimized. According to Park, the chip-to-package-to-pc board design flow needs to be performed in parallel because restraints on pc boards often place requirements on package design, while package requirements can in turn constrain chip design, both of which are ignored by current designs flows.

Serge Leef, Mentor’s vice president of new ventures and general manager of the company’s System-Level Engineering division, invited the automotive industry to adopt the EDA design methodology for on-board electronics.

According to Leef, the typical automobile today has up to 60 electronic control units (ECUs), up to 10 different data networks, several megabytes of memory and miles of wiring—all of which could be better designed by EDA-like software.

“Software components are like VLSI macros and standard cells; ECUs are like physical areas on the layout onto which IC blocks are mapped; signal-to-frame mapping is like wire routing,” said Leef.

New software tools are needed, according to Leef, which can copy the EDA methodology but be optimized for solving the simultaneous conflicting constraints in automotive electronics, permitting analysis and optimization of designs in order to reduce the number of test cars that have to be prototyped.

In perhaps the boldest presentation at ISPD, keynote speaker Louis Scheffer, a former Cadence Design Systems Inc. Fellow who is now at Howard Hughes Medical Institute, proposed adapting EDA tools to model the human brain. Scheffer described the similarities and differences between the functions of VLSI circuitry and biological neural networks, pointing out that the brain is like a smart sensor network with both analog and digital behaviors that can be modeled with EDA.

EETimes.com – Point/Counterpoint: Whats the right path for litho?

EETimes.com – Point/Counterpoint: Whats the right path for litho?.

Back in 1997, Intel led the formation of EUV LLC, a consortium that planned to commercialize extreme ultraviolet lithography by 2005. Advanced Micro Devices, IBM, Infineon and Micron were among the companies that signed on to the effort.

EUV was supposed to have replaced conventional optical lithography by now. But optical lithography is still driving the semiconductor engine, while EUV now is targeted for early production in 2012-or perhaps 2015 or 2016, depending on who’s offering the estimate. Some say it may never work.

Others are pushing for nanoimprint, maskless lithography or an emerging technology called self-assembly. And there are those who hope to extend today’s optical lithography indefinitely.

Was EUV the wrong bet for the industry? If so, what should it be working on instead? And who will benefit in the long run?

During the recent SPIE Advanced Lithography conference and other events, EE Times posed these questions to lithography experts and executives. Here are their responses.

Yan BorodovskyYan Borodovsky Intel Corp. senior fellow and director of advanced lithography at Intel’s Technology and Manufacturing Group

(Though it originally pushed for EUV, Intel is now weighing a mix-and-match lithography strategy.)

“I think complementary lithography is the right direction [for future IC designs]. . . . 193-nm lithography is the most capable and most mature technology that can meet both fidelity and cost-of-ownership requirements, but it has a weakness in terms of resolution. Complementing 193 nm with a new technology might be the best cost-of-ownership, performance and fidelity solution. The complementary technology could be either EUV or e-beam lithography.

“I think introducing EUV as a complementary technology has its challenges for high-volume manufacturing. Introducing multibeam e-beam as a complementary technology [also has its challenges].

“NAND flash makers have a much higher probability of introducing something like EUV before we do. Logic actually has more degrees of freedom in terms of layout, design rules and restrictions. So I can see why Samsung will be more aggressive to deploy EUV. They have no choice but to go to smaller wavelengths, higher NA [numerical apertures] and a K1 of 0.25.”

Dan HutchesonG. Dan Hutcheson CEO of market research firm VLSI Technology Inc.

“I think the industry is going in the right direction. It’s a lot better in this decade than in the last decade. I remember in the 1990s, when everything was on the [next-generation lithography] road map and no one would pull anything off.

“Meanwhile, we have an ongoing business that allocates so many dollars for R&D every year. And if you look out there for future nodes, you need to have two to three alternatives over your existing technology to make sure you can go down Moore’s Law.

“As a last resort, e-beam will always write fine geometries. The downside is that it violates Moore’s Law. Imprint is a very interesting technology; the technology needs to be developed. EUV, too.

“Then we have the existing technology, which is double patterning. But [if I’m a chip maker] I am going to spend a lot of money on [double patterning], because now my litho tool productivity is basically cut in half. So my cost per wafer doubles. And I am going to need twice as many tools, which is great for the equipment industry.”

Burn LinBurn Lin Senior director of the micropatterning division at Taiwan Semiconductor Manufacturing Co. Ltd.

“The industry is betting too much on one horse. I think it’s dangerous to bet on one horse. A lot of people know that.”

Chris MackChris Mack Consultant and “gentleman scientist”

“It’s always risky to bet on one technology that is high risk and not pursue others simultaneously. And I think it’s been a little bit out of whack that we’ve invested too much in trying to make EUV successful and getting too emotionally attached when you say, ‘We’ve got to make sure we’re not distracted by these other technologies, so we’re going to make sure that only EUV is the one we focus on.’ I don’t have a lot of complaints that EUV got a lot of funding. What I’ve got a complaint about is when people try to limit the other options that are the competitors.

“I am an ‘optical forever’ guy. I am a big proponent of doing more [research] on line-edge roughness. I think longer-term research on subassembly is something we should be doing. It was very premature to give up on some of the high-index materials development. If we have stayed the course, I think those high-index materials would have been there to extend double patterning another generation.”

Hans PfeifferHans Pfeiffer Proprietor of HCP Consulting Services

“If you remember, there have been quite a number of alternatives in lithography. One of them was X-ray, a large program that was supposed to extend lithographic capability beyond optical lithography. But optical lithography never fell off the cliff. And that’s the case today. However, I think we’re seeing the cliff a little bit closer now, and that’s what mobilizes all of these additional resources to finally come up with a practical alternative or solution.

“There are sure no winners right now. That’s the reason why many different technologies are being pursued. The top priority is still to further work on 193 nm and extend that to the absolute. This provides some time for EUV, which is the next major contender.

“But are we headed in the wrong direction? There are many different directions being pursued, but none has really so far exceeded EUV. Most large semiconductor companies are pretty much counting on EUV to be there.

“EUV always looked like the impossible dream. But there are tremendous resources behind it. Is EUV late? Yes. Everyone understands that lateness is not only inconvenient, but it’s also expensive.

“Maskless lithography is struggling to regain a certain level of interest in the industry. E-beam had a very successful period and then basically went under. It did not keep up with Moore’s Law.”

Kurt RonseKurt Ronse Director of the lithography department at IMEC

“I think we’re going in the right direction because there are not many alternatives at this moment; [we] either stop scaling or continue to push EUV.

“A lot of progress has been made on EUV. It’s not a done deal; there is a lot of work to be done. [But] in my opinion, the gap between EUV and the alternatives has increased during the last year. All of the other alternatives did not make much progress. They also had difficulties in getting funds. For the alternatives, it will be very challenging to hit their targets. The alternatives have to focus on 16 or 11 nm, because they have some ways to go. If they keep focusing on 32 nm or maybe 22 nm, they will miss their targets.”

Wally RhinesWalden Rhines Chairman and chief executive of Mentor Graphics

“Computational lithography [including OPC and other resolution enhancement techniques] is what will save us from the [soaring costs] of steppers. Computational lithography represents the biggest TAM [total available market] for EDA in the last decade.”

Dan RubinDan Rubin Venture capitalist with Alloy Ventures

“It is increasingly apparent that EUV is not able to leverage the conventional optical lithography infrastructure. The novel innovation required across an unestablished supply chain for EUV sources and reflective masks, and defect inspection continues to require herculean efforts, significant funding and schedule adjustments. If a complete technical solution is assembled in time, the suggested costs will make EUV unaffordable for advanced memory device adoption.

“I [am] a believer in imprint lithography for the memory market. The progress Molecular Imprints has made on less than a $100 million total investment is incredible, and the pace of performance improvements continues unabated. The usability of their CMOS tools and the throughput of their hard drive tools are technically impressive. If they had received a fraction of the dollars and industry attention that have been spent on EUV, they would have sub-32-nm CMOS production tools today.”

Mark Mmelliar-SmithMark Melliar-Smith CEO of nanoimprint lithography vendor Molecular Imprints Inc.

“The industry [has] restricted its vision. It is focusing much, much more on a single solution. I think that’s bad. “If MII had a month’s worth of EUV funding in the past year, we could have moved a long way to solving our remaining issues in the semiconductor market and been ready for production in 12 to 18 months.”

Kazuo UshidaKazuo Ushida President of the Precision Equipment Co. at Nikon Corp.

“For small-volume production, EUV looks very promising. But . . . EUV will be late for the 22-nm half-pitch road map. EUV will appear later, maybe by 16 nm. We have no metrology tools. It will take two years to develop the mask tools.”

SOI Consortium Launches SOI IP Portal – 2010-03-23 12:03:00 | Semiconductor International

SOI Consortium Launches SOI IP Portal – 2010-03-23 12:03:00 | Semiconductor International.

David Lammers, News Editor — Semiconductor International, 3/23/2010

The relative lack of intellectual property (IP) on silicon-on-insulator (SOI) has been rated by designers as the top barrier to using the technology. That prompted the companies in the SOI Industry Consortium to “get to work, so we could give the chip designers no excuse” for not taking advantage of SOI’s performance and power advantages, said Horatio Mendez, executive director of the group.

Today, the consortium is announcing its “Ready for SOI Technology” program, which will bring IP into a readily accessible SOI Portal, hosted on the ChipEstimate.com site now owned by Cadence Design Systems. The site will allow designers to download SOI-proven IP from IBM, ARM and Cadence, among others. Mendez said Boeing, which employs a large SOI chip design team in Colorado for military/aero applications, as well as Synopsys, recently decided to participate as well.

Synthesizable IP can be used on SOI technology without major alterations, and ARM has developed a physical IP library targeted to SOI. The new SOI Portal adds the ARM 1176 MPU core, but not the ARM Coretex processor core as of yet. IBM’s PowerPC cores are a processor option as well. Significantly, IBM’s SOI embedded DRAM is part of the SOI Portal. Design teams that choose to use the eDRAM, for example, would then negotiate a license with IBM, he said.

Initially, the designs would be targeted to IBM’s 45 nm foundry SOI process.

The SOI Portal will be demonstrated at the SOI Jump Start training event, planned for April 28, withonline participation or in-person attendance at the Cadence auditorium in San Jose.

Adam Traidman, general manager at Cadence, said ChipEstimate.com has >26,000 registered SoC designers, providing access to >200 IP suppliers and foundries.

Mendez said not all the IP that a cellphone chip design team might want is in the SOI Portal now, though a digital TV design team, for example, is likely to have all that it requires. “We are just getting started with this. As the momentum increases, more and more companies will join, including service providers. The other pieces will follow as the SOI marketplace demands them,” he said.

Membership in the SOI Industry Consortium currently includes AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Freescale Semiconductor, GlobalFoundries, IBM, IMEC, Infotech, Innovative Silicon, Kanazawa Institute of Technology, KLA-Tencor, MEMC, Mentor Graphics, MIT Lincoln Laboratories, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian.