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IMEC prepares industry for introduction of vertical transistors

IMEC prepares industry for introduction of vertical transistors.

According to industry sources attending the IMEC Technology Forum in Leuven, Belgium, the chip industry is currently preparing for the introduction of vertical transistors. Shang-yi Chiang, senior vice president of research and development at TSMC said that the company has already decided to use a vertical transistor structure at the 14nm node.

“We looked at the basic device physics, and came to a decision that we cannot use a planar structure at the 14nm node. With a vertical transistor we have better control of the channel,” said Chiang. TSMC will move from 28nm to 20nm, and then to the 14nm generation by the middle of this decade.

IMEC has also now opened the additional 1,200m2 of its cleanroom, which adds 50% to the facility that was opened five years ago. The added space was included to accommodate the NXT: 3100 EUV tool expected to be installed at IMEC by the end of 2010.

IMEC’s Thomas Hoffmann, director of the Front End of the Line (FEOL) program, said, “Today we are getting a lot of questions about FinFETs from the fabless companies that participate in our Insite program.” TSMC’s plans, as well as persistent rumors that Intel may adopt vertical transistors at the 22nm node, are driving the preparation efforts, he added.

“One challenge we and our partners have is unraveling how a gate-last technology on FinFETs will work. For companies moving to FinFETs at either the 22 or 16nm nodes, they want to know what the implications for high-k/metal gate if they go to a non-planar structure,” Hoffmann said in an interview at the IMEC facilities in Leuven.

The gate-last approach, first adopted by Intel at the 45nm node and also selected by foundry TSMC for its 28nm high-k process, has several advantages, Hoffmann said. The PMOS threshold voltage appears to be more stable with the gate-last approach, and an additional strain is achieved on the silicon channel in the PMOS transistor when the polysilicon replacement is removed. However, the gate-first camp, which includes GlobalFoundries, IBM, and the other members of the Fishkill Alliance, argue that the gate-first approach delivers a smaller die size than the gate last approach. Several companies which rely on foundries are now conducting shuttle runs to compare the performance and area of the competing approaches to high-k deposition.

“For low-power logic at 28nm, the gate-first approach can definitely meet the technology targets,” – Junctionless transistor is ready for 20-nm node, says researcher – Junctionless transistor is ready for 20-nm node, says researcher.

LONDON — Professor Jean-Pierre Colinge of Tyndall National Institute (Cork, Ireland), co-author of the paper Nanowire transistors without junctions that was published by Nature Nanotechnology recently, has said that junctionless transistors could be implemented commercially at around the 20-nm manufacturing node.The junctionless transistor is based on use of control gate around a silicon nanowire. The gate can be used to modulate the resistance of the nanowire and to “squeeze” the electron channel to nothing, thus turning off the device. Doping is used to produce p- and n-type FETs but there are no steep dopant gradients nor junctions, which promises simplified manufacturing.

Such a major change in the structure of the fundamental electronic device could be expected to require a great deal of independent research. An introduction at or around 20-nm would require companies to switch more or less immediately. However, a switch to the junctionless transistor could fit in with previously forecast moves by the industry away from planar transistors and towards FinFETs and multi- and wrap-around gate structures.

Speaking to EE Times by telephone Professor Colinge said: “It’s not shown in the Nature paper but we have made a silicon nanowire measuring about 10 nanometers by 10 nanometers. Now there is a rule of thumb that the gate length should be about twice the nanowire dimensions to avoid short channel effects. I think junctionless transistors could intersect with ITRS [International Technology Roadmap for Semiconductors] at 20-nm.”

Professor Colinge continued: “The junctionless transistor could compete now but it will take time for semiconductor companies to get used to the idea. People are scared of the high doping levels.”

According to the paper published in Nature Nanotechnology dopant levels of between 2 x 10^19 and 5 x 10^19 atoms per cubic centimeter were used. The high doping levels are required to ensure a high current drive and good source and drain contact resistance, the paper states.

But Professor Colinge pointed out that the junctionless transistor scales far better than a conventional transistor which will need to implant and control complex dopant gradients and profiles in diminishing distances. “The junctionless device does scale better. You still need the high resolution etching but you don’t have to scale the gate oxide as aggressively as you do on a regular device,” he said.

He also said that while the most recent paper does not address the issue, there is no reason why silicon junctionless transistors should not be amenable to induced strain to increase electron mobility. At the same time the junctionless approach could also be applied to materials other than silicon. “Yes it is applicable to other materials such as compound semiconductors,” Professor Colinge said.

Another difference between a conventional transistor and a junctionless transistor is that the junctionless device is a normally-on device, although this is made more complex by use of doped gate materials, Professor Colinge said. But he stressed that for the purposes of logic, memory and small signal operation there is no difference to a conventional transistor. “So far as we know the devices are interchangeable and there are no implications for the layout of logic,” he said.

The research presented in the Nature paper was partly paid for by Tyndall’s participation in two European funded projects Nanosil and EuroSOI+. – Intel’s Gargini pushes III-V-on-silicon as 2015 transistor option – Intel’s Gargini pushes III-V-on-silicon as 2015 transistor option.

LONDON — A presentation prepared by Paolo Gargini, Intel’s director of technology strategy, to give to the Industry Strategy Symposium Europe, held in Dublin, Ireland, earlier this week, stressed Intel’s progress in adding compound semiconductor layers to silicon as a means of continuing scaling and reducing power consumption.

Gargini, also chairman of the International Technology Roadmap for Semiconductors (ITRS), said in the presentation that the inclusion of III-V materials is a 2015 transistor option that could deliver either three times the performance of silicon at the same power consumption, or deliver the same performance as silicon at one-tenth the power consumption. However, integration of a thin compound semiconductor transistor channel with conventional silicon manufacturing would be the key to adoption.

While exceptional progress has been made in silicon to get to 32-nm, Gargini indicated in his slides that progress is coming only with more and more complicated additions to the basic silicon manufacturing process, such as the increased amounts of strain necessary to increase the electron mobility above its natural value; and the possible use of 3-D structures such as FinFETs.

Multigate FinFETs have advantages in improved electrostatics and a steeper sub-threshold slope, but Gargini put question marks against such things as parasitic resistance and capacitance and a layout methodology.

“Increase mobility in the transistor channel leads to higher performance and less energy consumption,” said Gargini on the slide, adding, “compound semiconductors have higher electron mobility than silicon; indium antimonide is highest of all.” Where gallium arsenide has 8 times higher mobility than silicon, indium arsenide is 33 times higher and indium antimonide is 50 times higher.

In the presentation Gargini laid out a few alternatives for integration. One method would be to include indium antimonide quantum-well FETs on a semi-insulating gallium arsenide substrate. Both depletion- and enhancement mode devices are possible.

As an alternative Gargini outlined progress in integrating an InGaAs quantum-well FET with a high-k dielectric gate stack. Gargini highlighted a series of papers presented by Marko Radosavljevic of Intel to the International Electron Devices Meeting (IEDM) over the years 2007 to 2009. This illustrated progress in developing the NMOS, PMOS transistors and, in December 2009, the high-K metal gate.

Gargini’s final conclusion was: “The advancement in non-silicon semiconductors deposited on silicon substrates could enable a new family of low power devices in the future.”

8_Griffin-TEL3D-WorkshopNov07.pdf (application/pdf 객체)

8_Griffin-TEL3D-WorkshopNov07.pdf (application/pdf 객체).

  • New high mobility materials will be needed to
    continue scaling progress
  • Germanium is a very promising material
    Low temperature processing is viable with Ge
  • Many opportunities exist for novel devices enabled
    by low temperature processing

2_R.Harris_SEMATECH.pdf (application/pdf 객체)

2_R.Harris_SEMATECH.pdf (application/pdf 객체).

2007 Stanford 3D workshop_1_Nishi_Stanford.pdf

WebCite query result.

5_M_GuillomIBM FinFETs for the 22 nm technology.pdf (application/pdf 객체)

5_M_GuillomIBM FinFETs for the 22 nm technology.pdf (application/pdf 객체).