Posts Tagged ‘ 28nm ’

TSMC’s Chiang Sees History on Side of Gate-Last High-k Approach – 2010-02-10 16:40:37 | Semiconductor International

TSMC’s Chiang Sees History on Side of Gate-Last High-k Approach – 2010-02-10 16:40:37 | Semiconductor International.

TSMC’s decision to adopt a gate-last approach to high-k deposition was informed by history, said S.Y. Chiang, in charge of R&D at the foundry. Two decades ago, companies tried to use the same gate electrode for both N- and PMOS transistors, a method that was soon abandoned, Chiang said. After a series of face-to-face meetings, TSMC’s design rules for its high-k process are being accepted by its largest customers.

David Lammers, News Editor — Semiconductor International, 2/10/2010

Last summer, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) made a surprising decision to use a gate-last deposition method for the high-k/metal gate stack of its 28 nm transistors. TSMC’s decision to use a replacement metal gate (RMG) technique was guided by history, said S.Y. Chiang, the senior vice president at TSMC in charge of R&D.

S.Y. Chiang (021010-ShangYiChiang.jpg)S.Y. Chiang, senior vice president, TSMCTwo decades ago, the semiconductor industry went through a similar tussle, when early CMOS developers tried to use an N+ poly gate for both the N-channel and P-channel devices. “When the industry began to do PMOS, companies found an N+ poly gate doesn’t work well,” Chiang said. “It was difficult to lower the Vt, so some people tried to add a counter dopant into the active region of the silicon channel to try to match the Vt. That caused a lot of problems, and made gate control and SCE (short channel effects) much worse.”

The gate-first approach to high-k ran into similar Vt control problems, Chiang said. Efforts to use capping layers improved gate-first performance, but a gate-first cap-layer process “gets very, very complicated and difficult to do,” he said. Two decades ago, for one technology generation, companies also tried to adjust the Vt for both NMOS and PMOS. “We went through exactly the same step when in our history we tried to use N+ poly,” Chiang said.

Asked about the restrictive design rules (RDRs) required for the gate-last method, Chiang said TSMC has been working with the layout teams at its largest customers to adjust to the gate-last high-k flow.

“With the gate-last technology, we do have some restrictions,” he said. “There is difficulty in planarizing it. However, if the layout team is willing to change to a new layout style, then they can get a layout density that is as good as with the gate-first approach. Not better, but the same. And it is not that difficult.” With high-k, Chiang added, “everybody — the process people as well as the layout people — need to adjust the way they do things in order to make the products competitive.”

TSMC’s design services team is working with the layout engineers at its largest customers. Chiang said they have demonstrated that with the appropriate alterations the IP cell libraries can achieve an equivalent layout density as with the gate-first approach. “Some people at first complained a lot, saying there would be a large density gap if they used the TSMC RDRs,” he said. “But after face-to-face meetings, the gate-last technique has been very well accepted.”

TSMC’s customers also appreciate what Chiang said is “a side effect” of using the gate-last approach: higher strain for the PMOS transistors.

TSMC plans to offer its first 28 nm processing by the middle of this year, using an SiON gate stack. “At 28 nm, that is the generation we push oxynitrides to the limit,” Chiang said. “We won’t continue to use oxynitrides after that — the transition has to happen somewhere.” The SiON process does have a cost advantage, and Chiang said customers who are not so concerned about gate leakage can move quickly to the 28 nm generation with the oxynitride process. “When it comes down to leakage, the customers who emphasize gate leakage have got to make the switch to high-k.”

TSMC high-k (021010-TSMCHKMG.jpg)TSMC will use its 28 nm SiON process to shake out issues not related to high-k/metal gate deposition. (Source: TSMC)

After the 28 nm SiON process moves into production at the end of the second quarter, TSMC will work to “clean off” any issues relating to interconnects, contacts, design rules and other issues. “That way, when we offer the HKMG process later in the year, we can be more focused on solving the HKMG process issues,” Chiang said.

Asked if the 28 nm generation promises to be a challenging one, Chiang said, “Some generations are relatively easier. For example, the transition from 90 to 65 nm had a very low risk. I do certainly believe 40 to 28 is very definitely a high-risk one, and we are preparing for that. We are preparing for all the possible scenarios. Reliability is a risk, and yield control. But we are working hard to prepare. Between 2006 and 2009, our headcount doubled, so I am pretty confident we will make this next generation a successful one.”

Chiang predicted the industry will coalesce around the gate-last method. “I do believe the gate-first people will change to gate last at the 22 nm node,” he said. “I am not criticizing them. But I think they will change. Unless they can find some very innovative way to adjust the threshold voltage without a lot of high cost, they will have to change.”

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TSMC to Start Production of 28nm Chips in Q4 2010 – X-bit labs

TSMC to Start Production of 28nm Chips in Q4 2010 – X-bit labs.

TSMC Tops Off Fab 12 Production Facilities

[01/20/2010 10:11 AM]
by Anton Shilov

Taiwan Semiconductor Manufacturing Company this week topped off its Fab 12 manufacturing facility. The new fab will allow TSMC to significantly boost output of chips produced using leading-edge fabrication processes that carry higher price tag. Besides, TSMC also announced that it would start production of chips using 28nm fabrication technology in Q4 2010.

Fab 12, Phase 4 and 5 are TSMC’s latest generation of production facilities designated for research and development as well as initial volume production. Phase 4 began volume production in third quarter of 2009, while construction began on Phase 5 at the end of 2009. Phase 5 is expected to begin volume production in the third quarter of 2010 to satisfy urgent recent increases in customer demand.

“The topping of our Fab 12, Phase 5 facility, and our plans to rapidly move in equipment and begin volume production there in the third quarter of this year is another example of our competitiveness in providing steadfast support for customers,” said Mark Liu, TSMC’s senior vice president of operations.

In addition to volume production of 28nm products, Fab 12, Phase 5 will also serve as the base for research and development of 22nm and more advanced process technologies. Currently, TSMC is conducting R&D for 28nm and 22nm process technologies at its Fab 12, Phase 1 and 2 facilities, and will hand 28nm technology to the Phase 5 facility for volume production in the Q4 2010.

By the fourth quarter of the year TSMC will have three versions of 28nm process technology ready, including those with silicon oxinitride/poly (SiON/Poly) dielectrics and high-K metal gate (HKMG) technology.

To meet customer needs, and in addition to capacity expansion at Fab 12, TSMC will also begin construction on Fab 14, Phase 4 located at its Tainan site. Groundbreaking is scheduled following the end of Chinese New Year, with the facility complete and ready for equipment move-in at the end of this year. These capacity expansion and technology development projects all attest to TSMC’s determination to provide steadfast support for its customers, the firm indicated.

In order to meet capacity and R&D needs, as well as strengthen TSMC’s technology leadership, the world’s largest contract maker of semiconductors began a large-scale recruitment campaign in January, and expects to hire more than 3000 semiconductor-related staff, primarily engineers. Considering that the market of semiconductors has still not fully rebounded, massive recruitment as well as capacity increases seem to be a result of increased competition from Globalfoundries, which not only has excellent production facilities, fine process technologies and plans to expand leading-edge manufacturing foundries, but also rich investors from Abu Dhabi emirate.