Posts Tagged ‘ 3D ’

EETimes.com – What’s the impact of 450-mm and EUV delays?

EETimes.com – What’s the impact of 450-mm and EUV delays?.

SAN JOSE, Calif. — Another analyst sees delays for 450-mm fabs and extreme ultraviolet (EUV) lithography–a possible sign that Moore’s Law is in danger of slowing down.

On Thursday (Jan. 21), IC Insights Inc. indicated that there could be delays for two chip-scaling enablers: 450-mm fabs and EUV. Another emerging chip-scaling technology, 3-D devices based on thru-silicon vias (TSVs), remains in the embryonic stages and is ”overhyped,” said Trevor Yancey, an analyst with IC Insights.

Gus Richard, an analyst with Piper Jaffray & Co., also sees delays for 450-mm fabs and EUV. ”We believe that the transition to EUV will (be) challenging at best, unaffordable at the worst and likely significantly delayed,” Richard said in a new report. ”The alternative cost reduction path is larger wafers (450-mm). However, equipment companies are unwilling to fund the R&D for 450-mm development.”

What does that all mean? Perhaps a slowdown in the two-year process technology cycle. ”The underlying economic engine of the semiconductor industry is Moore’s Law and the price elasticity it provides. If the cadence of Moore’s Law slows, we think the growth rate of the semiconductor industry would slow as well,” he warned.

The current recession has delayed the possible transition to the next-generation 450-mm wafer size. 450-mm fabs were supposed to happen in the 2012-to-2014 time frame.

There are some return-on-investment (ROI) issues for fab tool makers. Simply put, the fab tool customer base for 450-mm is too small. The R&D is too costly. ”We estimate that a 450-mm fab in 5-10 years will cost somewhere between $8 billion and $12 billion. In our view, only 2 to 5 companies that will be able to make the transition to a 450-mm due to the high cost,” Richard said.

EUV is also in trouble. On the lithography front, today’s immersion lithography technology is enabling devices down to the 3x-nm node, maybe even the 2x-nm node. Lithography is the crucial technology that drives scaling or Moore’s law, he said.

EUV is supposed to be inserted at the 16-nm logic node in 2013. IC Insights believes EUV will be delayed and may be inserted at the 13-nm node in 2015 or 2016.

”The transition to EUV lithography may take longer and cost more than is expected,” Richard warned. ”NAND and DRAM suppliers will need a production EUV tool by 2012 or 2013 and Intel would like to have EUV by 2014. We estimate that ASML will ship 4 or 5 beta tools in 2010, and it has indicated that these tools will be ready for production in 2012. However, based on our conversations with industry contacts, many believe that EUV will not be ready until 2014 or 2016.”

So what will the industry do instead? ”We believe that the current generation of immersion lithography tools will allow Intel to move to 16-nm and NAND flash suppliers to move to 22-nm, the foundries to move to 28-nm and DRAM manufacturers to move to the 2x-nm nodes,” he said.

”Based on our conversations with lithography experts, double or triple patterning in combination with computational lithography could extend immersion lithography to the 2x-nm node for most manufacturers,” he said. ”We believe that Intel will be able to push immersion lithography to 16nm. However, the extension of immersion to 22-nm and below is likely to add to the cost and complexity of the current immersion lithographic process, potentially making immersion at advanced nodes uneconomical.”

Not all agree, namely ASML Holding NV and Nikon Corp. Both are developing EUV tools.

”ASML is making the bet on EUV; we believe that it is a bold and high stakes bet. We believe that it is too early to predict EUV’s success or failure and more will be known as beta systems are installed in the second half of 2010,” Richard pointed out.

8_Griffin-TEL3D-WorkshopNov07.pdf (application/pdf 객체)

8_Griffin-TEL3D-WorkshopNov07.pdf (application/pdf 객체).

  • New high mobility materials will be needed to
    continue scaling progress
  • Germanium is a very promising material
    Low temperature processing is viable with Ge
  • Many opportunities exist for novel devices enabled
    by low temperature processing

7_Endoh_TohokuUniv.pdf (application/pdf 객체)

7_Endoh_TohokuUniv.pdf (application/pdf 객체).

  • vertical MOSFET and stacked vertical MOSFET in comparison with planar and other non planar MOFET like FinFET.
  • vertical MOSFET –> floating body surrounded gate transistor (SGT)

6_J.W. Lee_Samsung.pdf (application/pdf 객체)

6_J.W. Lee_Samsung.pdf (application/pdf 객체).

  • LEG technology easily able to obtain single c-Si layer
    over oxide and successfully implemented to 3-D
    stacking structure
  • Tr. characteristics on LEG Si film show the excellent
    performance and distribution
  • LEG SRAM with 3-level cell stacking has the extremely
    low Stand-by leakage current (0.3uA / Mb)
  • => LEG Process is one of highly promising technologies
    for stacked memory devices with manufacturability

4_BeSang.pdf (application/pdf 객체)

4_BeSang.pdf (application/pdf 객체).

2_R.Harris_SEMATECH.pdf (application/pdf 객체)

2_R.Harris_SEMATECH.pdf (application/pdf 객체).

2007 Stanford 3D workshop_1_Nishi_Stanford.pdf

WebCite query result.

Qualcomm’s Nowak: 3-D Faces Cost Issues

Qualcomm Director of Advanced Technology Matt Nowak outlined the cost and technology challenges facing 3-D interconnects in a speech at an IEEE 3-D IC conference. “If this technology adds more than 10% to final costs, it will not be widely used in high-volume wireless technology,” he said.
Phillip Garrou, Contributing Editor — Semiconductor International, 10/6/2009
In a plenary speech at the IEEE 3-D IC conference in San Francisco, Qualcomm Inc. (San Diego) Director of Advanced Technology Matt Nowak said 3-D interconnects face plenty of issues that must be dealt with before the benefits of the approach can be realized.
“While 3-D with TSVs currently has significant industry momentum, more development work is needed to bring this technology to high-volume manufacturing,” Nowak said, adding that TSV (through-silicon via) development and characterization needs to move to leading-edge CMOS, containing strained transistors, ultralow-k dielectrics, and thin die.
Although 300 mm equipment installations are beginning worldwide and test chips are being reported, Nowak noted that a number of issues need to be overcome, including:
• Lack of 300 mm lines in production
• Lack of standard process flows
• Unproven yield/reliability
• Unclear supply chain handoffs
• Lack of consensus on cost targets

The attraction of TSVs is apparent for mobile wireless devices looking for low-cost solutions that improve power efficiency while enhancing performance in terms of bandwidth/milliwatt. Noting that Qualcomm today relies on stacked bare die using wire bond and flip-chip, Nowak said 3-D TSV technology would enable “new architectural solutions that can only be realized with such high-density tier-to-tier connections.”
Many potential 3-D IC users are clamoring for immediate standardization, but Nowak said it may be too early to standardize the technical solutions. Standards eventually will be needed for:
• Nomenclature/definitions
• TSV size, tier thickness, via fill material
• Tier-to-tier pin locations and assignments
• Microbump and passivation materials, properties and geometries
• Reliability test methods
• Metrology

Nowak indicated that foundry TSVs, in which the vias are created in the middle of the process flow, made the most sense and would probably end up being the high-volume manufacturing technology of choice.
Although it is still not resolved where the handoff point will be between the foundry and the outsourced semiconductor assembly and test (OSAT) supplier, Nowak pointed out that handle wafer mounting and dismounting must be done by the same group.
After studying the the cost of ownership models of IMEC, Sematech and EMC-3D, Qualcomm derived its own preliminary economics and determined that the overall cost is dominated by post-fab backside processing. One of the technical conclusions the company reached from its cost modeling is that “thinner is better” — going from 50 µm to 20 µm thick layers could reduce the TSV module portion of the total cost by as much as 25% if the added thin wafer handling costs were not substantial.
Nowak said cost will determine the extent of 3-D IC product adoption. “If this technology adds more than 10% to final costs, it will not be widely used in high-volume wireless technology.”
picture device independent bitmap 111

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