Posts Tagged ‘ IMEC ’

IMEC prepares industry for introduction of vertical transistors

IMEC prepares industry for introduction of vertical transistors.

According to industry sources attending the IMEC Technology Forum in Leuven, Belgium, the chip industry is currently preparing for the introduction of vertical transistors. Shang-yi Chiang, senior vice president of research and development at TSMC said that the company has already decided to use a vertical transistor structure at the 14nm node.

“We looked at the basic device physics, and came to a decision that we cannot use a planar structure at the 14nm node. With a vertical transistor we have better control of the channel,” said Chiang. TSMC will move from 28nm to 20nm, and then to the 14nm generation by the middle of this decade.

IMEC has also now opened the additional 1,200m2 of its cleanroom, which adds 50% to the facility that was opened five years ago. The added space was included to accommodate the NXT: 3100 EUV tool expected to be installed at IMEC by the end of 2010.

IMEC’s Thomas Hoffmann, director of the Front End of the Line (FEOL) program, said, “Today we are getting a lot of questions about FinFETs from the fabless companies that participate in our Insite program.” TSMC’s plans, as well as persistent rumors that Intel may adopt vertical transistors at the 22nm node, are driving the preparation efforts, he added.

“One challenge we and our partners have is unraveling how a gate-last technology on FinFETs will work. For companies moving to FinFETs at either the 22 or 16nm nodes, they want to know what the implications for high-k/metal gate if they go to a non-planar structure,” Hoffmann said in an interview at the IMEC facilities in Leuven.

The gate-last approach, first adopted by Intel at the 45nm node and also selected by foundry TSMC for its 28nm high-k process, has several advantages, Hoffmann said. The PMOS threshold voltage appears to be more stable with the gate-last approach, and an additional strain is achieved on the silicon channel in the PMOS transistor when the polysilicon replacement is removed. However, the gate-first camp, which includes GlobalFoundries, IBM, and the other members of the Fishkill Alliance, argue that the gate-first approach delivers a smaller die size than the gate last approach. Several companies which rely on foundries are now conducting shuttle runs to compare the performance and area of the competing approaches to high-k deposition.

“For low-power logic at 28nm, the gate-first approach can definitely meet the technology targets,”

EETimes.com – IMEC forms ‘more-than-CMOS’ alliance with TSMC

EETimes.com – IMEC forms ‘more-than-CMOS’ alliance with TSMC.


EE Times

LONDON — Luc van den Hove, president and chief executive officer of IMEC (Leuven, Belgium), has said the research institute has entered into a partnership with Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) to develop hybrid “more-than-Moore” process technologies and pass them on to the Taiwanese foundry.Although IMEC works with most leading chip makers on the leading-edge of CMOS materials and process development, there is tremendous scope for creating application-driven variants of CMOS at more mature nodes.

Speaking at the International Electronics Forum in Dresden, Germany, van den Hove said IMEC would develop CMORE platforms for specific applications. Hybrid processes could mix logic and memory with thermal, chemical and optical sensors, with bioelectronic interfaces, with photonics, microelectromechanical systems (MEMS) and RF circuits in BiCMOS processes.

While IMEC has created and is expanding a 300-mm pilot wafer fab for leading-edge research, it has an older 200-mm pilot line that is suitable for developing so-called CMORE processes.

“We will develop CMORE platforms for specific applications and have a partnership with for TSMC to take on the processes from there,” van den Hove told attendees at the conference.

Van den Hove said that for a major foundry like TSMC there was a chicken-or-egg problem in that it could not develop specialized processes until it was sure of volume demand and volume demand would not materialize without the existence of the process. IMEC was in a position to break that impasse and to work with customers in low volumes before passing the process over to TSMC as and when higher volumes of chips are needed.

Finding the sweet spot where an application-specific process appeals to a large number of customers, or at least a few customers who foresee high volumes, will be the key. Such areas could include medical electronics, consumer interfaces or instrumentation.

IMEC has appointed Kees den Otter, former president of TSMC Europe BV, to the position of vice president of emerging business, an apparent indication that IMEC intends to drive its CMORE program on a commercial basis.