Posts Tagged ‘ SOI ’

SOI Consortium Launches SOI IP Portal – 2010-03-23 12:03:00 | Semiconductor International

SOI Consortium Launches SOI IP Portal – 2010-03-23 12:03:00 | Semiconductor International.

David Lammers, News Editor — Semiconductor International, 3/23/2010

The relative lack of intellectual property (IP) on silicon-on-insulator (SOI) has been rated by designers as the top barrier to using the technology. That prompted the companies in the SOI Industry Consortium to “get to work, so we could give the chip designers no excuse” for not taking advantage of SOI’s performance and power advantages, said Horatio Mendez, executive director of the group.

Today, the consortium is announcing its “Ready for SOI Technology” program, which will bring IP into a readily accessible SOI Portal, hosted on the site now owned by Cadence Design Systems. The site will allow designers to download SOI-proven IP from IBM, ARM and Cadence, among others. Mendez said Boeing, which employs a large SOI chip design team in Colorado for military/aero applications, as well as Synopsys, recently decided to participate as well.

Synthesizable IP can be used on SOI technology without major alterations, and ARM has developed a physical IP library targeted to SOI. The new SOI Portal adds the ARM 1176 MPU core, but not the ARM Coretex processor core as of yet. IBM’s PowerPC cores are a processor option as well. Significantly, IBM’s SOI embedded DRAM is part of the SOI Portal. Design teams that choose to use the eDRAM, for example, would then negotiate a license with IBM, he said.

Initially, the designs would be targeted to IBM’s 45 nm foundry SOI process.

The SOI Portal will be demonstrated at the SOI Jump Start training event, planned for April 28, withonline participation or in-person attendance at the Cadence auditorium in San Jose.

Adam Traidman, general manager at Cadence, said has >26,000 registered SoC designers, providing access to >200 IP suppliers and foundries.

Mendez said not all the IP that a cellphone chip design team might want is in the SOI Portal now, though a digital TV design team, for example, is likely to have all that it requires. “We are just getting started with this. As the momentum increases, more and more companies will join, including service providers. The other pieces will follow as the SOI marketplace demands them,” he said.

Membership in the SOI Industry Consortium currently includes AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Freescale Semiconductor, GlobalFoundries, IBM, IMEC, Infotech, Innovative Silicon, Kanazawa Institute of Technology, KLA-Tencor, MEMC, Mentor Graphics, MIT Lincoln Laboratories, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian.


Technology@Intel · A look at the future of the transistor from the Solid State Devices and Materials Conference (SSDM)

Technology@Intel · A look at the future of the transistor from the Solid State Devices and Materials Conference (SSDM).

A look at the future of the transistor from the Solid State Devices and Materials Conference (SSDM)

posted by Kelin Kuhn on October 30, 2009

I’m writing this on the plane from Narita airport to Portland as I return from  giving the plenary talk at the Solid State Devices and Materials conference (SSDM), in Sendai Japan.  It is always exciting to visit these device conferences to see the myriad of new options that are being discussed for next generation transistors.

Before I get into the technical details, I have a few fun stories to share about my trip.  I arrived a little early, so I could have the weekend to tour Tokyo.  Much of my time in Tokyo was spent figuring out the subway/train system.  In all the excitement, I managed to lose my wallet on the subway, and to my surprise and delight  – it was returned a few hours later (with all the money intact).  I was deeply impressed as I doubt that would happen in New York!   Another adventure was with a Japanese toilet at Tokyo institute of technology. Japanese toilets are quite complicated (among other things, they play music) with a number of interesting features (which I will not describe here, you’ll need to go to Japan to check).  This was one of the more complicated ones, and in looking for the flush button, I pushed a green button that looked reasonable.  Well, it was an alarm button.  A horn sounded, the lights turned on and off and so on and so on.   Made me deeply suspicious of all buttons for the rest of the trip.   At this point, I hoped my adventures were over, but no.    I had a most interesting night on the 12th floor of the hotel when the typhoon Melor passed over (as a side note, I began to feel jinxed, because I ran into Melor a second time when in California a few days later after it had crossed the Pacific).

Anyway, enough of the light stuff, now let’s discuss the meat!   SSDM is a big conference (~1000 people) where the various conference sessions include papers ranging from energy systems to organic semiconductors.   Of the most interest to me were the sessions focusing on the various approaches for continued gate scaling through improved short channel control.

High-k metal gate is the primary path for improved short channel control.  Intel leads the pack in this area, with its recent 32nm announcement demonstrating successful second-generation high-k metal gate (  Note that much of the industry is trying to “catch up” to Intel, with significant discussion industry-wide on the correct architecture for the gate (gate-first or replacement, one metal or two, and so on) with representative SSDM papers such as those presented by Drs. Ikeda, Kim and Fukutome.   There is also significant research on gate materials, shown with papers such as those from Drs. Kadoshima and Inumiya.   Another area of strong research is fundamental physics of the HiK-metal gate materials system, with SSDM papers such as those by Drs. Hsieh and Shimizu.

Advanced device architectures are another path for improved short channel control.  This include ultra thin body (UTB) devices, vertical thin body devices (for example, trigate and Finfet), and lateral nanowire devices.   UTB devices are the simplest of the new architectures, with short channel control offered by a thin body, and with fabrication being an extension of historical processing.   An additional advantage of UTB devices is excellent random variation due to the undoped depleted body (several interesting SSDM papers in this area, including the papers of Drs. Andrieu  and Lee).  The problem is that UTB devices are expensive (SOI is NOT cheap), and quite sensitive to variation in the body thickness (changes in body thickness affect VT from quantum effects, and also impact DIBL and SS)).  In addition, the thin body creates high external resistance and makes it extremely difficult to strain the devices.

Multiple gate (MuGFET) devices such as FinFETs or Trigates are a longer term path for improved short channel control.   These devices mitigate many of the variation issues with UTB devices (because the desired fin width is greater than 2X of the equivalent body thickness in an UTB device.) HOWEVER, the non-planarity of these devices represents significant challenges in fabrication.    Dr. Veloso’s paper nicely explored many of these challenges in some detail.    Lateral nanowire devices are next in the logical sequence, again offering significant advantages for short channel control, but at the cost of challenging fabrication.  While nanowires offer further short channel benefit, they have all the issues of FinFETs, along with a host of new issues, many of which were explored in papers from Drs. Chen, Seike, Lee and others.

I had a lot of fun, and learned some new things.   As a wonderful closure for the trip, as we were leaving Narita airport (after pushback and just as the plane started to taxi on its own) all the line service folks (the people who fuel the plane etc.) lined up and waved and then bowed the plane off.  “What a wonderful custom,” I thought, as I waved back.

SOI Reduces Dynamic Power, Wafer Costs Coming Down

Silicon-on-insulator (SOI) technology is seeking to penetrate the high-volume market for mobile Internet devices and smart phones. An ARM paper at last week’s IEEE International SOI Conference compared power consumption levels for bulk and SOI. And wafer supplier Soitec said it anticipates volume wafer prices in the $500 range.
By David Lammers, News Editor — Semiconductor International, October 12, 2009
At last week’s IEEE International SOI Conference in Foster City, Calif., researchers from ARM Ltd. (Cambridge, UK) reported on power savings for a 45 nm silicon-on-insulator (SOI) test chip based on a widely used ARM core. The paper was the result of an ARM collaboration with Soitec (Grenoble, France).
The comparison, however, was between a simulation of a bulk 45 nm CMOS low-power (LP) implementation, and physical extractions from a 45 nm SOI test chip. The ARM team said the comparison resulted in a ~40% power savings for the SOI test chip running at 500 MHz, the frequency level that may be required for upcoming smart phones and mobile Internet systems.

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Static power consumption increases modestly when chip temperature increases during operation.

For the past decade, SOI technology has been seeking to break into the high-volume mobile IC space, based on the lower capacitances possible with the buried oxide substrates. Although servers and other high-performance systems have been able to bear the cost of SOI wafers, companies making price-sensitive mobile systems thus far have avoided SOI technology on cost grounds, for the most part.
“Our cost structure is already achieving the target we believe is the right one to penetrate the mobile market,” said Jocelyne Wasselin, director of marketing and business development at Soitec. Customers can anticipate seeing volume wafer prices in the $500 range, she said, down sharply from two years ago when Soitec was quoting ~$800 price levels.
At the SOI conference, the ARM test chip was based on the widely used ARM 1176 core and IBM’s 45 nm SOI process. It was compared with an unidentified bulk 45 nm CMOS technology. The SOI results were based on extractions from silicon, but the ARM team said it was “awaiting the bulk CMOS parts from the foundry.” Due to lack of bulk silicon results, the ARM team said “45 LP simulation results are used to compare with the 45 SOI silicon. At the 500 MHz target frequency, 45 SOI enables a 38% total power reduction compared with 45 LP, despite the high leakage difference, thanks to much lower dynamic power and Vdd scaling.”

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SOI power consumption, measured at three different operating voltages, remains under control at relatively high frequencies. (Source: ARM)

Moreover, the 45 nm LP implementation resulted in a core area of 1.38 mm2, including both logic and memory, while the 45 nm SOI test chip resulted in a 1.28 mm2 core, a 7.3% area reduction.
Although the SOI test chip had lower active power, the static (leakage) power was much higher. Static power was 0.17 mW for the bulk CMOS simulation, and 9.3 mW for the SOI test chip. “The leakage difference is aligned with what we expected from a low power versus high performance technology comparison. It is worth noting that the leakage difference is strongly reduced between 45 LP and 45 SOI when increasing the temperature from 25ºC to 125ºC (from 57× down to 6×),” the Grenoble-based ARM team reported.
If the 45 SOI core frequency is increased to 600 MHz, the total power consumption reaches 75 mW, still 28% below 45 LP running at 500 MHz. The 45 SOI enables a 20% speed improvement over 45 LP along with a 28% power reduction,” the ARM team said.
Horacio Mendez, executive director of the SOI Industry Consortium (Boston), argued that bulk low-power CMOS technology “cannot reach the performance targets for the next-generation mobile Internet devices (MIDs) and smart phones.” Though the general, or G, process offerings “can reach the performance levels for these markets, it is at a significantly higher power consumption, a >50% power increase.”
Mendez said in order for the foundry bulk G processes to reach the performance levels required for MIDs and smart phones, “the technology needs to add considerable complexity — principally deep N well/P well implants and shallow trench isolation complexity — which leads to increased cost. Bulk technology cost is increasing faster than for SOI.”
Mendez said that when the smaller die size is factored in, the total cost difference between SOI and bulk will be in the single digits for the 32/28 nm generation, and will “begin to reach parity at 22 nm.”
IEDM has fully depleted slant
For leading-edge technology developers, fully depleted SOI technology is an active area of interest. At the 2009 International Electron Devices Meeting (IEDM), beginning Dec. 7 in Baltimore, an IBM team will report results from devices fabricated on extremely thin SOI (ETSOI) CMOS, with silicon carbon (SiC) stress techniques. The IBM team claims record low variability for low-power system-on-a-chip applications.
Also at IEDM, a Leti-Soitec-STMicroelectronics team will report on a hybrid fully depleted SOI/bulk high-k/metal gate platform for LP multimedia applications. The Grenoble-based team will report ring oscillator delay improvements of ~15% compared with bulk 45 nm devices.
An IEDM paper given by researchers from the Indian Institute of Technology-Bombay and Infineon Technologies will compare simulated results from planar and non-planar SOI devices. “Non-planar devices perform poorly in comparison to ultrathin body (UTB) planar SOI MOSFETs, and are not the ideal choice for SoC applications,” the paper’s abstract concludes.