Posts Tagged ‘ TSMC ’

TSMC to make FinFETs in 450-mm fab

TSMC to make FinFETs in 450-mm fab.

At the SPIE Advanced Lithography conference here, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) outlined more details about its 450-mm fab plans. SAN JOSE, Calif. – At the SPIE Advanced Lithography conference here, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) outlined more details about its 450-mm fab plans.

The silicon foundry giant hopes to process 14-nm FinFET devices in full production on 450-mm wafers by 2015 or 2016, said Shang-Yi Chiang, senior vice president of R&D at TSMC.

As reported, Intel, Samsung and TSMC are pushing hard for 450-mm fabs. Intel has already announced two ”450-mm ready’’ fabs. The fab tool vendors are warming up to 450-mm development, but most are still behind schedule with the technology. Some believe that 450-mm will cause confusion in the supply chain.

Recently, TSMC said it plans to install its first 450-mm line in Taiwan by 2013 to 2014.  It will process wafers at the 20-nm node on 450-mm substrates. Many of the details were not disclosed when TSMC made that initial announcement.

In an interview at SPIE after his keynote, Chiang elaborated on those plans. Initially, TSMC hopes to install a 450-mm pilot line in Fab 12 in Hsinchu, Taiwan. The line will process wafers at the 20-nm node. It hopes to get the pilot line up and running by 2013 to 2014.

Then, TSMC plans to bring up its first 450-mm production fab in Taichung, Taiwan, which will process devices at the 14-nm node. The Taichung plant is called Fab 15.

At 14-nm, TSMC plans to make a switch in transistor structures. At the 20-nm node and above, TSMC will continue to use traditional planar transistors based on bulk CMOS. At 14-nm, the company plans to make the switch from bulk CMOS to FinFET structures, he said.

So, the company will produce 14-nm FinFETs in production in Fab 15. Production is slated for 2015 to 2016.

The TSMC technologist said 450-mm wafers enable a 2.25- to 2.40-fold productivity gain over 300-mm wafers. But he acknowledged there are several challenges with 450-mm, namely to get the equipment vendors on board.

At one time, most fab tool vendors were reluctant to invest in 450-mm. Many believe it is too expensive and there is little or no return-on-investment.

Now, fab tool vendors are warming up to the idea for several reasons. First, Sematech, which is leading the charge in 450-mm, is providing some funding for fab tool vendors in 450-mm. Second, the world’s largest chip makers are pushing hard for 450-mm and fab tool vendors don’t want to lose out on some business.

Chiang in a question and answer session said that ”the government would pay for half of the cost’’ of 450-mm tool R&D, but he did not elaborate.

”We see a bit more willingness on the part of equipment makers’’ to embrace 450-mm, said C.J. Muse, an analyst with Barclays Capital, in a recent report. ”We then think by 2016-2018, we will see adoption of 450-mm.’’

Lam Research Corp. is reportedly beginning to invest in 450-mm. Other fab tool vendors are also quietly developing tools, but 450-mm won’t be cheap.

Drop in the (450-mm) bucket
It could cost about $12 billion in R&D investments for 450-mm, Muse said. ”The move to 300-mm was very much more expensive than the prior wafer transitions. While estimates from VLSI/Sematech suggest the 125-mm transition cost only ~$250-300 million and the 150-mm transition ~$700 million, the 300mm cost ~$12 billion,’’ he said.

”It is assumed that the 450-mm transition will not be cheap, and clearly equipment companies are reluctant to pay the full tab. We will likely see a chicken and egg game, but we do expect chipmakers to help support the tool development efforts with equipment companies, at the same time, sharing some of the higher dollars received in the current golden era of capital intensity,’’ he said.


Analysts’ take: Samsung incites “foundry wars” with 32nm HKMG volley – Solid State Technology

Analysts’ take: Samsung incites “foundry wars” with 32nm HKMG volley – Solid State Technology.

by James Montgomery, news editor

June 14, 2010 – Samsung’s announcement that it has completed testing of its 32nm high-k/metal gate architecture, ramping to volume possibly by year’s end — and following quickly with a 28nm version — has the industry buzzing about a possible reshaping of leading-edge semiconductor foundry manufacturing.

Ana Hunter, VP foundry at Samsung Semiconductors, filled in some of the details for SST. The Samsung 32nm process is a gate-first HKMG structure based on the IBM common platform. An SoC application processor “designed for maximum testability” — the same one used by Samsung for its 45nm low-power process, for an apples-to-apples comparison — improves dynamic power reduction by 30% and leakage power by 55% (thanks to things like power gating, multi-threshold voltages, multi-channel lengths and adaptive body biasing techniques). It incorporates an ARM 1176 core, with physical core library, cells, memory compilers, etc. designed by ARM. Also included is a Synopsys IP macro, plus other Samsung-designed IP basically used to qualify the ecosystem process; Samsung also is working with EDA partners (e.g. Synopsys, Cadence, Mentor) to make sure everything works with design kits and tools that its customers already use. Everything at 32nm HKMG can be migrated to 28nm, Hunter said; design rules are shrinkable with recharacterization and timing.

Gate-first HKMG is easier to implement as a transition from a traditional poly/SION structure, Hunter explained. The construction of the gate and transistor remain the same, though the materials are different (i.e., a high-k gate oxide instead of oxynitride); a metal gate is inserted, and then poly on top of that — and the rest of the flow is “basically the same as previous generation structures,” she said. Compared with gate-last HKMG, gate-first also is “much simpler” to implement from a process migration standpoint in terms of IP implementation, and fewer restrictive design rules (gate-last requires CMP around the gate structure). Gate-first enables good logic density shrinking — “we can maintain 50% shrink from 45nm to 32nm because there’s not as many restrictive design rules,” Hunter said. This makes the process particularly good for mobile applications, as it’s cost-effective and “very good on gate leakage — >100× improvement from 45nm to 32nm.”

After early process development w/ the alliance, Samsung installed the technology in its S line in Korea (on which the company also does LSI work), completed qualification and reliability testing (wafer-level, package-level, 1000 hour stress testing) with materials manufactured on the S line, to improve yield and manufacturability, noted Hunter. Tape-out will be in the next few months. with primarily prototyping and customer sampling in 2H10, and production in early 2011 (or possibly pulled into the very end of 2010). “The process is frozen,” Hunter said; what remains is “getting yield up, getting more tools qualified, bringing up the manufacturability side of things.” She also confirmed that the 28nm HKMG version “is still on schedule to be production-ready in 1H11.” (That’s about in line with what Samsung said late in 2009, and Hunter reiterated in April in a podcast with SST‘s Debra Vogler, that 32nm/28nm HKMG was in “preparation” for volume production with tapeouts later in the year and moving “very quickly to 28nm.”)

Ana Hunter, VP foundry, Samsung Semiconductors

Why do both 32nm and 28nm; Samsung’s foundry differentiators; CPA pros/cons

Pros/cons of its HKMG process being based on the IBM Common Platform Alliance: “We develop the process jointly, provide customers the ability to multisource in different factories with competitive business models…Of course we compete for business, but we think the foundry market is a big market, growing all the time.” With another company based on the same technology, and options to do other things (e.g. additional modules, customize processes) — “having that baseline being able to source at both suppliers, working together to ensure GDS compatibility, is a major competitive advantage. There’s plenty of business out there for us both.”

What’s the strategy to compete with TSMC: “Obviously we have not been in the foundry business as long as TSMC has, and we’re nowhere near as big. Our strategy is to be very competitive in advanced technology nodes. To that end, we are very focused on achieving leadership in advanced nodes — not just development but taking it to high-volume manufacturing, because we have the financial capability to do so.”

“Getting into the business to be a second source is not our intention.”

Why strongly pursue both 32nm and 28nm HKMG: The strategy is to be “all-in at 32nm and smooth the way for 28nm,” Hunter explained. “We thought it was important to meet the needs of customers who want 32nm now, an advantage in time-to-market, then follow close with 28nm.” Planting the HKMG flag first at 32nm “makes us a leader…we think that’s important to have competitive position there, to invest in these technologies, to bring to production in high-volume fabs,” she said. And getting HKMG under its belt early and fast, and ramped to volume, is particularly important so that customers are “comfortable with manufacturability and cost savings,” especially for low-power target end-applications like mobile devices, she noted. “Having 32nm in production will help us a lot with the learning curve, making 28nm a much smoother transition,” Hunter said.

Differentiators for Samsung’s foundry business: If a customer needs help with a design, Samsung’s Hunter sees this as a differentiator: “We do that work in silicon and real products, and feed that learning back into design flows that we can provide our foundry customers.” Samsung also has ASIC services for customers who want to have backend design work done. “The line between ‘ASIC backend’ and foundry is becoming fairly gray and fuzzy; customers are more and more seeking help on the design side [which is] getting very complex,” Hunter said. “DFM built into design is something we’re experts in.”

Supporting foundry with capex. Note that Samsung’s recent capex blitz for 2010 included about $1.8B for its system LSI operations, within which the foundry business is a subset. (Hunter offered no definition as to how that’s split up — Gartner’s Dean Freeman suggested the foundry portion could be up to $1B.) Hunter did say that the new investments are “very beneficial for our foundry business,” being in advanced technology nodes and 300mm lines “where our foundry business is concentrated.” Also, Hunter noted that the $1.8B pie is only for manufacturing lines — and suggested there’s another 8T won (almost US $7B) in R&D capex budget that could be tapped as well.

Analysts’ take: Finally, a foundry horse-race!

Samsung isn’t the biggest foundry, and the question of who’s “first” with HKMG is still up for grabs — but certainly its announcement of production-ready 32nm HKMG and a 28nm version soon to follow has complicated the equation for leading-edge semiconductor manufacturing options.

TSMC has been talking about HKMG but has set its bar at what traditionally have been viewed as “half-nodes,” e.g. 40nm and 28nm, notes Joanne Itow with Semico Research. TSMC’s 40nm process offered “a slightly different formula for power and performance” — but there were some openly known yield issues that caused headaches and poor publicity, she added. Gartner’s Freeman suggested no foundry has “completely ditched” 32nm HKMG in favor of 28nm — TSMC is running an abridged version for those who want it, and GF has a 32nm offering as well, but “they don’t talk a lot about it as they are both moving to the half-node where the foundry money is.”

So which foundry will be first with 32nm/28nm HKMG, and when? Samsung says it will have 32nm HKMG ready by late 2010 or early 2011 — earlier this year it identified Xilinx as the first customer for 28nm HKMG, and Hunter told SST that “there are others” both existing and new customers (but she wouldn’t name names). Qualcomm is another leading-edge customer for Samsung, and so is Apple (Samsungfabbed a chip for the iPad); “You also might see Infineon with a device or two,” Freeman suggested. Meanwhile, GlobalFoundries will have a 32nm HKMG version ready in 4Q10, which is a MPU for AMD using an SOI process — though it’s unclear if/when a 32nm HKMG foundry process will be available. In January TSMC said Qualcomm would tape out a 28nm process in mid-2010, but wasn’t specific whether that would be HKMG or SION. Almost a year ago it said it would start ramping 28nm HKMG process (first a HP version, then LP) in 3Q/4Q10. TSMC and GF roadmaps are very similar, Freeman said, so rollouts could be separated by only a month or two.

“Due to the way roadmaps are announced it will be difficult to tell who will really be first until someone announces a customer is shipping in some sort of volume,” Freeman said.

The greater message may be that the foundry sector is finally becoming a horse race. Though TSMC will likely ramp its HKMG option first, its lead on others has notably shrunk, says Freeman. “What we have at 32nm/28nm is the real beginning of what I have been calling the foundry wars” — GlobalFoundries and the Common Platform Alliance trying to unseat TSMC, and TSMC firing back. “The differentiation will be who can provide the design service I need, Meet my capacity requirements, and hit my technology roadmap,” Freeman said.

Judging just based on research, “I believe the foundries are neck and neck — and that includes Samsung,” said Itow. For actual deliverables, TSMC would still lead the pack but with GF and Samsung right behind. “I’d compare this to a horse race that requires a photo finish to determine the winner,” she said. “And actually, there probably aren’t any losers in this race — the customers are provided more variety with lots of proven technology.”

IMEC prepares industry for introduction of vertical transistors

IMEC prepares industry for introduction of vertical transistors.

According to industry sources attending the IMEC Technology Forum in Leuven, Belgium, the chip industry is currently preparing for the introduction of vertical transistors. Shang-yi Chiang, senior vice president of research and development at TSMC said that the company has already decided to use a vertical transistor structure at the 14nm node.

“We looked at the basic device physics, and came to a decision that we cannot use a planar structure at the 14nm node. With a vertical transistor we have better control of the channel,” said Chiang. TSMC will move from 28nm to 20nm, and then to the 14nm generation by the middle of this decade.

IMEC has also now opened the additional 1,200m2 of its cleanroom, which adds 50% to the facility that was opened five years ago. The added space was included to accommodate the NXT: 3100 EUV tool expected to be installed at IMEC by the end of 2010.

IMEC’s Thomas Hoffmann, director of the Front End of the Line (FEOL) program, said, “Today we are getting a lot of questions about FinFETs from the fabless companies that participate in our Insite program.” TSMC’s plans, as well as persistent rumors that Intel may adopt vertical transistors at the 22nm node, are driving the preparation efforts, he added.

“One challenge we and our partners have is unraveling how a gate-last technology on FinFETs will work. For companies moving to FinFETs at either the 22 or 16nm nodes, they want to know what the implications for high-k/metal gate if they go to a non-planar structure,” Hoffmann said in an interview at the IMEC facilities in Leuven.

The gate-last approach, first adopted by Intel at the 45nm node and also selected by foundry TSMC for its 28nm high-k process, has several advantages, Hoffmann said. The PMOS threshold voltage appears to be more stable with the gate-last approach, and an additional strain is achieved on the silicon channel in the PMOS transistor when the polysilicon replacement is removed. However, the gate-first camp, which includes GlobalFoundries, IBM, and the other members of the Fishkill Alliance, argue that the gate-first approach delivers a smaller die size than the gate last approach. Several companies which rely on foundries are now conducting shuttle runs to compare the performance and area of the competing approaches to high-k deposition.

“For low-power logic at 28nm, the gate-first approach can definitely meet the technology targets,”

TSMC versus SAMSUNG « Daniel Nenni

TSMC versus SAMSUNG « Daniel Nenni.

According to the EETimes – “The leading-edge foundry market is up for grabs, as several vendors have stumbled or been victims of the shakeout “. According to people who actually work with the foundries, like myself, the leading edge foundry market will continue to be dominated by TSMC and GlobalFoundries is the “dark horse”Samsung is now and will always be an IDM, with the foundry business being a diversion at best.

The EETimes also claims that TSMC “stumbled and had yield issues at the 40-nm node.”Again not true. TSMC has more than 80% of the 40nm market with 60+ products in production. TSMC forecasts 40nm accounting for 20% of overall revenues at the end of 2010, compared to 9% in the fourth quarter of 2009. Other foundries would be lucky to stumble into numbers like that!

TSMC Fab 12 is currently capable of producing 80,000 12-inch equivalent wafers on 40nm every quarter and will double that by the end of 2010. TSMC’s other 300-mm GigaFab, Fab 14, can also be used to meet future 40nm demand.

The widely reported TSMC 40nm yield problems were focused on GPUs. GPU products are bleeding edge technologies that drive process development, including half nodes. There are (5) GPU players with market share: Intel,  Nvidia, AMD/ATI, S3, and SiS. Intel is an IDM, the rest manufacture at TSMC. Why TSMC you ask? Because GPUs are the single most difficult product to yield and TSMC is the only foundry that can accommodate the insanely competitive GPU market.

According to Ana Hunter, Samsung Semiconductor Vice President of Foundry Services, after 4+ years of trying “Samsung’s share of the foundry business is not as big as we want, but it takes time to put the pieces in place and ramp designs.” Prior to Samsung, Hunter spent 9+ years at Chartered Semiconductor, which was bought by GlobalFoundries last year for pennies on the invested dollar. Hunter stated that “The foundry business is part of our core strategy” and highlighted 6 reasons why Samsung believes it will succeed:

  1. Capacity – Samsung plans to double its production of chips for outside customers every year until it rivals market leader TSMC. ( Wow, good luck with that!)
  2. Resources – Samsung is one of the few companies that has the resources to compete at the high-end of the foundry market. (Intel, IBM, TSMC, GFI….)
  3. Leading Edge Technology – Samsung is ramping 45-nm technology at a time when TSMC and others are struggling in the arena. (Oh no she di’int!)
  4. Leading Edge Technology part II – Samsung will be one of the first foundries to roll out a high-k/metal-gate solution. The technology will be offered at the 32- and 28-nm nodes, which will be rolled out this year. (TSMC and GFI will go straight to 28nm HKT this year)
  5. Leading Edge Technology part III – Unlike rival TSMC, Samsung is using a gate-first, high-k technology, TSMC is going with gate-last. We think that gate-first is best suited for today’s needs. (I defer to TSMC on this one, they have forgotten more about the foundry business than most will ever know.)
  6. Ecosystem – Samsung has put the EDA pieces in place for the design-for-manufacturing puzzle. (A puzzle analogy, really?)

Now let me highlight 6 reasons why I believe Samsung will not succeed:

  1. Business Model – The Foundry business is services centric, the IDM business is not. This is a serious paradigm shift for Samsung.
  2. Customer Diversity – Supporting a handful of customers/products is a far cry from supporting the 100’s of customers and 1,000′s of products TSMC does.
  3. Ecosystem – An open ecosystem is required which includes supporting commercial EDA,Semiconductor IP, and Design Services companies of all shapes and sizes.
  4. Conflict of Interest – Pure-play foundries will not compete with customers, Not-pure-play foundries (Samsung) will. Would you share sensitive design, yield, and cost data with your competitor?
  5. China – The Chinese market represents the single largest growth opportunity for the foundry business. TSMC has a fab in Shanghai and 10% control of SMIC (#4), UMC (#2) has control of China’s He Jian (#11), and Samsung does not even speak Mandarin.
  6. Competition – The foundry business is ultra competitive, very sticky, and product dumping will not get you from #9 to #1.

Just my opinion of course, feel free to share yours. – IMEC forms ‘more-than-CMOS’ alliance with TSMC – IMEC forms ‘more-than-CMOS’ alliance with TSMC.

EE Times

LONDON — Luc van den Hove, president and chief executive officer of IMEC (Leuven, Belgium), has said the research institute has entered into a partnership with Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) to develop hybrid “more-than-Moore” process technologies and pass them on to the Taiwanese foundry.Although IMEC works with most leading chip makers on the leading-edge of CMOS materials and process development, there is tremendous scope for creating application-driven variants of CMOS at more mature nodes.

Speaking at the International Electronics Forum in Dresden, Germany, van den Hove said IMEC would develop CMORE platforms for specific applications. Hybrid processes could mix logic and memory with thermal, chemical and optical sensors, with bioelectronic interfaces, with photonics, microelectromechanical systems (MEMS) and RF circuits in BiCMOS processes.

While IMEC has created and is expanding a 300-mm pilot wafer fab for leading-edge research, it has an older 200-mm pilot line that is suitable for developing so-called CMORE processes.

“We will develop CMORE platforms for specific applications and have a partnership with for TSMC to take on the processes from there,” van den Hove told attendees at the conference.

Van den Hove said that for a major foundry like TSMC there was a chicken-or-egg problem in that it could not develop specialized processes until it was sure of volume demand and volume demand would not materialize without the existence of the process. IMEC was in a position to break that impasse and to work with customers in low volumes before passing the process over to TSMC as and when higher volumes of chips are needed.

Finding the sweet spot where an application-specific process appeals to a large number of customers, or at least a few customers who foresee high volumes, will be the key. Such areas could include medical electronics, consumer interfaces or instrumentation.

IMEC has appointed Kees den Otter, former president of TSMC Europe BV, to the position of vice president of emerging business, an apparent indication that IMEC intends to drive its CMORE program on a commercial basis. – Seven things that surprised us at TSMC event – Seven things that surprised us at TSMC event.

SAN JOSE, Calif. — I’ve attended TSMC’s Technology Symposiums for many years.

Like past years, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) presented a dizzying array of technology and new processes at this year’s event. It presented new roadmaps in CMOS processes, analog, MEMS, RF and other areas. Here were the surprises and my observations at the one-day event:

1. Morris Chang. Last year, Chang, 79, regained the CEO title at TSMC. He’s running the ship amid a chaotic time in the IC industry. But during a keynote this week, Chang seemed as vibrant and feisty as he was when I first met him in the early 1990s. More importantly, he seems to have restored customer confidence after the company experienced a snafu at the 40-nm node. And with Chang at the helm, the company is far more aggressive in terms of capital spending, R&D and hiring. In fact, Chang said TSMC will expand its workforce from 25,000 today to 29,000 by year’s end.

Simply put, TSMC is back on track–much to the chagrin of its rivals.

2. We want capacity! During the keynote, Chang on several occasions said that the company is expanding its fab capacity. Why? The company has been sold out of fab capacity for some time and customers are screaming for more capacity. But my feeling is that TSMC is still being careful about its capacity expansion plans.

Last year, margins were relatively lousy amid the IC downturn. This year, it is enjoying the boom cycle–and margins. So why spoil the party? On the other hand, TSMC has some new competitors–all of which would love to take same business away from the foundry king.

3. Nerves of steel. TSMC has always been a confident company. Almost too cocky. And a little arrogant at times, which is not a bad trait if you’re the best in the business. In the past, though, it never really respected its competitors. I remember when it even dismissed IBM and Samsung.

To me, there is a new sense of uneasiness at TSMC: It is finally taking notice of the competition. In fact, there is a new sense of respect for the competitors at TSMC. GlobalFoundries has emerged and Samsung is finally serious about the foundry business.

In recent times, TSMC left its rivals in the dust. However, TSMC stumbled at the 40-nm node with lackluster yields. It was a humbling experience. Now, the company has some real competition. Let the battle begin.

4. TSV delays? Chip scaling is showing no signs of hitting the wall–yet. But one alternative path–3-D technology based on through-silicon vias (TSVs)–continues to generate steam.

In years’ past, TSMC provided a roadmap for its TSV production efforts. At this year’s event, the company was low-key about TSVs. It didn’t provide a timeline to develop the technology, nor did it give us a real progress report. ”We’re still in the early stages” with TSVs, said Shang-yi Chiang, TSMC’s senior vice president of research and development.

Translation: Cost and complexity is still a problem with TSVs. Or perhaps TSV has been delayed at TSMC and elsewhere.

5. FinFET city. Seeking to take the lead in the silicon foundry business, TSMC will jump directly from 28- to the 20-nm “half node” process technology.

What’s after the 20-nm node? Chiang believes that 20-nm could be the last year that TSMC uses a CMOS planar process. After bulk silicon, TSMC is banking on the FinFET as the next-generation transistor. For years, TSMC has been looking at the FinFET, a double-gate transistor. The surprise is that TSMC appears to have already made a decision on that technology. Other leading-edge chip makers are still exploring multi-gate structures.

6. TSMC branded LEDs. In March, TSMC held a groundbreaking ceremony for an R&D center and wafer fab to develop and make light emitting diodes (LEDs) for lighting applications.

The move marks a major change at TSMC, which has until this point been focused on the foundry supply of integrated circuits. In fact, TSMC will not provide foundry services for LED makers. Instead, the company will develop and sell LEDs under the ”TSMC brand,” according to a TSMC spokesman. TSMC will not compete against its customers, the spokesman insisted.

7. Solar strategy. TSMC is still exploring its strategy in solar. Like LEDs, the company may sell solar panels and the associated modules under its own name, the company hinted. Don’t look for a solar foundry service. I don’t know for certain, but TSMC may be even mulling plans to jump into the utility business. – TSMC skips 22 nm, rolls 20-nm process – TSMC skips 22 nm, rolls 20-nm process.

SAN JOSE, Calif. — Seeking to take the technology lead in the silicon foundry business, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is putting a new spin on its strategy: After the 28-nm node, it plans to skip the 22-nm ”full node” and will move directly to the 20-nm ”half node.”

At its technology conference here, the world’s largest silicon foundry also provided details about its 20-nm CMOS process, which will be the company’s main technology platform after the 28-nm node. TSMC will also not offer an 18-nm process.

TSMC’s 20-nm process is a 10-level metal technology based on a planar technology. It will feature a high-k/metal gate scheme, strained silicon and newfangled ”low-resistance” copper ultra-low-k interconnects–or what it calls ”low-r.” For the 20-nm node, it will only offer a high-k/metal-gate scheme for the gate stack–and not a silicon dioxide option.

TSMC (Hsinchu) will continue to use 193-nm immersion lithography at 20-nm, but it will also deploy a double-patterning and source-mask optimization schemes. Unlike its previous processes in recent times–which focused on low power first–TSMC’s initial 20-nm process will be a high-performance technology. Following that process, it will roll out a low-power technology.

With the announcement, TSMC is seeking to gain an edge over its leading-edge rivals, such a GlobalFoundries, Samsung and UMC. Both Samsung and UMC have said little or nothing about their respective 2x-nm nodes.

By going to 20-nm, TSMC is leapfrogging one rival–at least on paper. Recently, GlobalFoundries Inc. said it is starting work on its 22-nm CMOS process, which is due out in the second half of 2012. TSMC is also looking at the second half of 2012.

In comparison, Intel Corp. is expected to be at the 22-nm node by the fourth quarter of 2011. As for which vendor is leading in the foundry race at 2x-nm, it’s unclear until a company ”beats the drum and announces they are in production,” said Dean Freeman, an analyst with Gartner Inc.

Meanwhile, TSMC is taking a different approach with its process nodes. In the past, TSMC marched down a predictable process path, as defined basically by the ITRS roadmap. Then, it would generally offer a ”half-node” process as a means to migrate customers to the next node.

As of late, TSMC generally pushed its customers to the half-node process, possibly as a means to differentiate itself. For example, TSMC rolled out a 32-nm process, but it will move customers over to the 28-nm technology.

At one time, it was widely believed that TSMC would offer a 22-nm node. ”22-nm was an option for customers, but we decided to skip it,” said Shang-yi Chiang, TSMC’s senior vice president of research and development. In an interview, Chiang said that the move to 20-nm creates a better gate density and chip performance to cost ratio than a 22-nm process technology.

At the 2x-nm foundry node, cost and complexity will continue to escalate for customers. In recent times, TSMC has provided process flows, design kits and intellectual property (IP) to help reduce foundry costs. ”Customers must engage with us at a much earlier stage” at 20-nm to reduce costs and complexity, Chiang told EE Times.

An IBM researcher recently warned of “design rule explosion” beyond the 22-nm node during a paper presentation earlier this month at the International Symposium on Physical Design (ISPD). Kevin Nowka, senior manager of VLSI Systems at the IBM Austin Research Lab, described the physical design challenges beyond the 22-nm node, emphasizing that sub-wavelength lithography has made silicon image fidelity a serious challenge.

TSMC’s 20-nm process features 10-level metal layers, although customers may typically use 6-to-8 layers, he said. The company continues to push bulk CMOS silicon at 20-nm, as it will not migrate to silicon-on-insulator (SOI) or other transistor structures such as FinFETs.

Chiang believes that 20-nm could be the last node that TSMC uses a planar structure. Following that node, possibly 14-nm, TSMC may be forced to go to a FinFET or a 3-D structure.

Like its 45-, 40-, 32- and 28-nm processes, TSMC will use 193-nm immersion lithography at 20-nm. At that node, it will likely use one or more forms of double patterning, source-mask optimization and other technologies. Its main lithography vendor is ASML Holding NV.

At that node, TSMC is also evaluating other lithography candidates, namely EUV and maskless. The foundry provider will initially go with 193-nm immersion at 20-nm production, but it may also deploy EUV or maskless in 2013-to-2014, depending on the viability of those technologies, he said.

ASML recently said that TSMC will take delivery of ASML’s extreme ultraviolet (EUV) lithography system. At some point, TSMC will take delivery of a TwinScan NXE:3100 tool from ASML. The NXE:3100 is a ”pre-production” EUV tool, said to have an NA of 0.25.

In addition, TSMC and Mapper Lithography BV recently claimed that Mapper’s multi-beam e-beam tool located on TSMC’s Fab 12 GigaFab is printing features so far unachievable with current immersion lithography. In 2008, TSMC and Mapper concluded an agreement according to which Mapper would ship its first 300-mm multiple-electron-beam maskless lithography platform for process development and device prototyping to TSMC.

At 28-nm, the company is supposed to roll out its first high-k/metal-gate scheme for the gate stack. At that node, it will also offer a silicon dioxide option. So far, TSMC’s high-k technology is progressing, he said.

Meanwhile, at 20-nm, TSMC will deploy its fifth-generation strain engineering technology and its second-generation high-k/metal-gate scheme. For 20-nm, TSMC will only offer a high-k/metal-gate technology. It will not offer a silicon dioxide scheme for the gate stack.

Originally, TSMC was planning to go with a gate-first high-k technology. Now, it will go with gate-last. There are two basic approaches to the next-generation gate stack in logic designs. IBM’s ”fab club” is using a gate-first approach, while Intel is deploying a rival replacement-gate or gate-last technology. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.

”The real key difference in the gate-last approach (is that) we use two different gate metals, one metal for the P channel and one metal for N channel. For the gate-first approach, we use the same metal for N and P channel. In gate-last, we can freely adjust voltage for both N channel and P channel. Gate-first has difficulty doing that. So that’s a major difference,” Chiang said in a recent presentation.

For years, TSMC has deployed low-k dielectrics, based on Applied Materials Inc.’s Black Diamond technology. At 28-nm, TSMC is using a carbon-doped oxide process with a ”k” effective number of 2.6.

At 20-nm, TSMC will use an in-house low-k material. the ”k” effective number will move to 2.3. ”Pushing low-k is very difficult,” due to the porous materials and packaging issues, he said.

So instead of pushing the constant, TSMC is taking another approach: It is moving to ”low-r” instead of low-k. ”We will lower the resistance rather than pushing the capacitance,” he said.

Going is towards lower resistance in the interconnect is ”not surprising,” said Gartner’s Freeman. ”You will also see new barrier seed materials at 20,” he said.

TSMC is currently shipping its 40-nm process. Then, it will move to the 28-nm node.

”The first node we’re going to release for the 28-nanometer will be we call the 28 LP (low-power). This is our poly gate and silicon oxide nitrate version. We will establish production at the end of June this year,” Chiang said in a recent presentation.

”The first high-k metal gate we call 28 HP for the high performance application will be introduce the end of September this year, and followed by three months later December will be the 28 HPL. This is the first high-k metal gate introduction for the low power application,” he said.

TSMC’s high-performance 20-nm process is slated to move into risk production in the third quarter of 2012, with volume production scheduled for the first quarter of 2013. Two quarters after the high-performance technology, TSMC is slated to roll out its low-power process.