Analog and RF Design Issues in High-k & Multi-Gate CMOS Technologies (IFX, 2009 IEDM 18.3) .PDF – Google Docs
HK related design
- 12bit ADC in 32nm HK CMOS : any small Vt variation should be handled by
- error correction by non-binary search algorithms can efficiently compensate for resolution and performance degradation due to hysteresis effects
- 1/f noise from HK now low enough
- Phase noise/power in VCO using HK/MG –> state of art.
Mug related design
- roughness of sidewall –> degrade noise and RF performance
- increased series resistance
- high fringing cap
- VCO, PL L–> show competitive jitter and phase noise/power FOMs
- LNA –> good noise and power matching behavior
- Self heating increases current consumption
- Better Short Channel control –> beneficial for output impedance, gain, Vt matching
Beyond Moore 