Posts Tagged ‘ 2009 IEDM ’

Analog and RF Design Issues in High-k & Multi-Gate CMOS Technologies (IFX, 2009 IEDM 18.3) .PDF – Google Docs

Analog and RF Design Issues in High-k & Multi-Gate CMOS Technologies (IFX, 2009 IEDM 18.3) .PDF – Google Docs.

HK related design

  • 12bit ADC in 32nm HK CMOS : any small Vt variation should be handled by
  • error correction by non-binary search algorithms can efficiently compensate for resolution and performance degradation due to hysteresis effects
  • 1/f noise from HK now low enough
  • Phase noise/power  in VCO using HK/MG –> state of art.

Mug related design

  • roughness of sidewall –> degrade noise and RF performance
  • increased series resistance
  • high fringing cap
  • VCO, PL L–> show competitive jitter and phase noise/power FOMs
  • LNA –> good noise and power matching behavior
  • Self heating increases current consumption
  • Better Short Channel control –> beneficial for output impedance, gain, Vt matching

Design Challenges for 22nm CMOS and Beyond (S.Barkar, Intel 2009 IEDM)


Past : segmented hardmacro functional block –> system is built using combination of those hardmacro with a bit of softmacro.

    • relied upon custom design methodology for higher performance and smaller area.
    • –> due to increasing design rule complexity, restrictions, and regularity –> little room to improve custom design
    • custom design more focus on local design rather than global design –> sub optimal in overall sense.
  • Future : System with soft macro only.
    • in 22nm and beyond is System Design with design automation at all levels.
    • Softmacro rather than hardmacro
      • described at a higher level of abstraction, such as an RTL description.
    • system can be built at a higher level of abstraction using these softcore functional blocks
      • processors, bus, other functional blocks
      • system is optimized using system level optimizer
    • physical design is optimized as well.
    • Custom design is limited to memory array, register files