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Gate First, or Gate Last: Technologists Debate High-k – 2010-03-10 15:41:15 | Semiconductor International

Gate First, or Gate Last: Technologists Debate High-k – 2010-03-10 15:41:15 | Semiconductor International.

David Lammers, News Editor — Semiconductor International, 3/10/2010

As high-k rolls out beyond Intel Corp.1 to both mobile and high-performance applications, the industry now faces a divided landscape.2 Intel and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) — the largest MPU provider and pure-play foundry, respectively — are backing the replacement metal gate (RMG) or gate-last approach. Their competitors — Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.), GlobalFoundries Inc. (Sunnyvale, Calif.), IBM Corp. (Armonk, N.Y.), and other members of the Fishkill Alliance — are using the gate-first approach, at least for the 28 nm node.3 United Microelectronics Corp. (UMC, Hsinchu, Taiwan) said it will use a hybrid approach employing a gate-last method for the more-difficult PMOS transistor.4

High k cover imageNo matter what deposition flow is used, high-k is offering benefits, which is why the stakes are so high for getting it right. Not only does high-k sharply reduce gate leakage, the gate capacitance scales with a thinner equivalent oxide thickness (EOT). Though mobility may be not quite as high as in a chip using a native oxide, cutting the EOT with high-k enables a shorter gate length and improves the drive current.

However, pressure is building on the gate-first approach. Some high-k experts argue that the high-temperature steps following the high-k dielectric and metal gate deposition cause the Vt to shift, affecting PMOS performance in particular. Others, including John Pellerin, director of technology at GlobalFoundries, argue that the gate-first approach requires less-restrictive layout design rules, provides for a smaller die size, and eases IP porting, while meeting the performance needs of customers at the 32/28 nm node.

“We are unequivocally committed” to the gate-first approach at 28 nm, Pellerin said. “The die size and scaling potential are very critical factors. We get a lot of feedback that people are seeking ease of migration” as they move to a high-k solution.

S.Y. Chiang, senior vice president at TSMC, said the semiconductor industry went through a similar discovery process two decades ago, when early CMOS developers tried to use an N+ poly gate for both the N-channel and P-channel devices.

“When the industry began to do PMOS, companies found an N+ poly gate doesn’t work well,” Chiang said. “It was difficult to lower the Vt, so some people tried to add a counter dopant into the active region of the silicon channel to try to match the Vt. That caused a lot of problems, and made gate control and short channel effects (SCE) much worse.”

With that history in mind, Chiang said the gate-first approach to high-k ran into similar Vt control problems. Efforts to use capping layers improved gate-first performance, but Chiang said a gate-first cap-layer process “gets very, very complicated and difficult to do.”

Asked about the restrictive design rules (RDRs) required for the gate-last method, Chiang said TSMC has been working with the layout teams at its largest customers to adjust to the gate-last high-k flow.

“With the gate-last technology, we do have some restrictions. There is difficulty in planarizing it. However, if the layout team is willing to change to a new layout style, then they can get a layout density that is as good as with the gate-first approach. And it is not that difficult,” he said, adding that “everybody — the process people as well as the layout people — need to adjust the way they do things in order to make the products competitive.”

Chiang said TSMC’s early 28 nm high-k customers are all large companies that are well-equipped to handle layout changes. “We have had face-to-face meetings, and our high-k strategy has been very well accepted. Later, we will offer more help to the layout people at our smaller customers.”

The fact that TSMC was willing to switch to a gate-last approach “says something about the performance advantage of the gate-last approach,” said Dean Freeman semiconductor manufacturing analyst at Gartner Inc. “Gate first gets you a little bit tighter layout, but TSMC must have seen something they didn’t like when they did their shuttle runs,” comparing the gate-first and gate-last wafers.

Thomas Hoffmann, an IMEC (Leuven, Belgium) high-k research manager, raised some of the performance challenges with the gate-first approach at the 2009 International Electron Devices Meeting (IEDM).5 In a follow-up interview, Hoffmann said the gate-first deposition method makes some sense for low-power devices that don’t require the ultimate in performance.

“For low-power companies, such as Renesas and others, gate-first is possibly the best trade-off. They don’t require all the low Vt‘s and high performance, which is harder to do with gate first. But as they proceed beyond 28 nm, companies will need the extra performance advantage that gate last will deliver.”

High k fig 11. Cap layers can improve the Vt of gate-first gate stacks. (Source: IMEC)However, for performance-oriented companies that require a lower Vt, Hoffmann said “gate last is a must for high-performance applications. IBM obviously must provide high-performance solutions, and I think they need to bring in additional tricks to achieve low Vt‘s with the gate-first approach. Those tricks have a cost in terms of process complexity or yield. At the end of the day, offsets are possible, but perhaps that is why the other companies in the Fishkill Alliance may be getting nervous.”

Although gate last requires careful control of the etching and CMP steps, gate first also has its process control challenges, Hoffmann said. One of the key steps in gate first is deposition of the capping layer either below or on top of the high-k to adjust the Vt. For example, a thin layer — <1 nm — of La2O3 is deposited on the NMOS devices to achieve the appropriate Vt. The lanthanum layer must be removed from the PMOS devices, which requires patterning with resists, careful etching to avoid damage, and other “highly selective” process steps, Hoffmann said. An Al2O3 capping layer on the PMOS devices is employed to control the Vt (Fig. 1).

“You want the benefit of lanthanum for NMOS, but then you have to remove it for the PMOS,” Hoffmann said. “It is not simple at all to remove resist over a material that is very thin to begin with, while avoiding damage to the capping layer. It requires proper control and selectivity.”

Glen Wilk, business unit manager for ALD and epitaxial products at ASM International NV (Almere, Netherlands), said technologists have been debating the performance, complexity and cost issues between gate-first and gate-last deposition for many years. “What I do see coming is that as the technology scales, it is playing more to the strengths of the gate-last approach. There is better ability to set and control the work functions, a better choice of electrodes due to the lower thermal budget. You get the Vt where you want it and get it to stay there.”

As the industry scales, users of the gate-first approach will find it “difficult to control the PMOS characteristics,” Wilk said. Getting the optimum PMOS work function will “get tougher as devices scale, as the thermal budget gets tighter. It will be tougher to make [gate first] work. There will be an industry-wide focus on gate last.”

The benefits of the gate-last approach, in terms of extra strain and overall work function control, make gate last the best option for both high-performance and low-power applications, Wilk said. “Memory companies may have a little more room to play with. They may be able to accept gate first for a while. It really is becoming important not only for the high-performance guys, but also for low standby power, to look at gate last.”

Taking a dual approach is not the way to go, Wilk said. “Foundries want to have one solution, not many solutions,” he argued. “If they use gate last for performance, they will find a way to make gate last work for low standby power. They need one way to manage. If we are going to get to it, let’s get to it. Let’s not keep trying to force an approach that is going against the sweet spot of gate last.”

Hans Stork, CTO at Applied Materials Inc. (Santa Clara, Calif.), said the gate-first approach requires a carefully controlled etch of the capping layers used to control the Vt, while the gate-last method requires expertise at metal deposition and CMP. “Extendibility wise, gate last appears to have the better long-term outlook.”

Stork notes that foundries are paying close attention to Intel’s 32 nm system-on-chip (SoC) process, which uses a 0.95 nm EOT high-k layer for the high-performance and low-power transistors. “Intel’s SoC process extends the gate-last, high-performance process to low-leakage applications and low-voltage operations,” he said. “It is in the sweet spot for cell phone chips.” Customers are watching how the gate-first vs. gate-last alternatives deliver on work function control, cost/productivity, and yields. Large fabless companies such as Qualcomm Inc. (San Diego) that compete in the cell phone space, Stork said, will demand that their foundry suppliers “match Intel’s performance so they can remain competitive.”

At IEDM, Qualcomm technology executives said they are “very comfortable” with the gate-last technology direction endorsed by TSMC last July. In January, Qualcomm said it also will use GlobalFoundries at the 28 nm node. That will set up a head-to-head competition between the Qualcomm cell phone applications processors made at TSMC with a gate-last high-k process, and the gate-first approach used at GlobalFoundries. The 40 nm Qualcomm-designed cell phone CPUs are high-performance chips, running at 1 GHz in the recently introduced Google smartphone, for example, while requiring mobile-appropriate levels of power consumption.

Mark Bohr, director of process architecture at Intel’s Hillsboro, Ore.-based technology and manufacturing group, said the Atom-based products that use the 32 nm SoC process6 may be about a year away, though the exact schedule depends on the product groups (Fig. 2).

High k 22. Intel’s 32 nm NMOS (left) and PMOS transistors have a gate pitch of 112.5 and use a second-generation high-k/metal gate technology.

Asked if the gate-last process results in a larger die size due to more restrictive design rules (RDRs), Bohr said Intel’s RDRs at the 45 nm node have nothing to do with the replacement gate technology, and everything to do with Intel’s desire to stick with non-immersion lithography. “The gridded design was not to enable our high-k/metal gate,” Bohr said, but to support dry lithography.

Zero interface layer

Researchers — including Intel’s Bohr — seem to agree that HfO2 will continue to be used as the base dielectric material for the medium-term future. Rather than switch to new materials with relatively modest increases in the dielectric constant, the industry is better off to improve on hafnium-based dielectrics, though some companies are attempting to tweak the HfO2 with proprietary additives.

Much attention is being paid to reducing the oxide interfacial layer, which, for example, can account for ~5 Å of a ~10 Å EOT gate insulation layer. “Most thinking in the industry now is how to optimize hafnium, rather than start another five-year quest for a new material,” said Paul Kirsch, manager of Sematech’s high-k program. “From a time and effort perspective, let’s improve the effective k, eliminating the SiO2 interface.”7

At IEDM in December, several papers on zero interface layer (ZIL) technology were presented, including a presentation from the IBM-led Fishkill Alliance, which has used the gate-first approach for the 32/28 nm generation.8 An IMEC ZIL paper at IEDM also used a gate-first approach (Fig. 3).

high k 33. An IMEC high-k/metal gate device with no interfacial layer. Indicated thicknesses are in nm. (Source: IMEC)

T.P. Ma, a professor at Yale University, said ZIL is attractive, but most of the scavenging agents require relatively high-temperature steps to remove the interface layer. That lends itself to the gate-first approach, which supports higher temperatures for the gate stack.

Ma said his understanding is that ZIL “requires a high-temperature chemical reaction” to successfully scavenge the SiO2 interface layer. The gate-first approach, for all of its Vt challenges, is designed to withstand high temperatures, Ma said, while the gate-last approach “tries to avoid” high temperature exposure. The IBM and Sematech ZIL results have been “a pleasant surprise” in that the 5 Å EOT layers have shown acceptable leakage characteristics, Ma said.

The early Sematech ZIL work did involve a gate-first deposition method according to Raj Jammy, vice president of materials and emerging technologies at Sematech. “The ZIL approach does not necessarily depend upon high temperatures, but depends on the oxygen scavenging species,” he said, adding that different species have different thermal processing needs in order to be effective (Fig. 4).

High k 44. An interface layer of 5 Å can account for one-half of the EOT. Sematech created a zero interface layer device in 2009. (Source: J. Huang et al., IEEE VLSI Symposium 2009, Sematech)

An IMEC researcher said, “Our approach to reaching a zero interface layer does indeed require a thermal budget. However, there are other ways of growing an interface-free gate-stack. So this in itself is not a reason for selecting one before the other.” He added that it should be possible to “combine the low EOT of the ZIL gate-first gate stack with an improved effective work function using replacement gate.”

There “is more to do” to improve on the dielectric material and to reduce capacitance of the metal electrodes, Bohr said. Asked about the merits of completely removing the interface layer, “My impression is that is not very useful,” partly because ZIL devices do not exhibit the best channel mobility. “If you create the right kind of interface layer, it doesn’t trap a lot of charge.”

Gartner’s Freeman said high-k/metal gate technology will be a critical differentiator between TSMC and GlobalFoundries, starting at the 28 nm node. One possibility is that IBM and GlobalFoundries will do a “very quick about-face” at the 22 nm node, adopting a gate-last technology. Another possibility is that the gate-first approach may prove more capable of removing the interface layer. “Interface control will be absolutely critical at 16 nm,” Freeman said.

References

1. J. Markoff, “Intel Says Chips Will Run Faster, Using Less Power,” New York Times, Jan. 27, 2007, p. 1.
2. D. Lammers, “Pressure Builds on Gate-First High-k,” Semiconductor.net, Dec. 9, 2009.
3. D. Lammers, “GlobalFoundries Adds Qualcomm, Supports Gate-First Technology at 28 nm Generation,” Semiconductor.net, Jan. 7, 2010.
4. G.H. Ma, et al., “A Novel ‘Hybrid’ High-k/Metal Gate Process for 28 nm High Performance CMOSFETs,” 2009 IEDM, p. 655.
5. T. Hoffmann, “High-k/Metal Gates: Industry Status and Future Direction,” 2009 IEDM Short Course.
6. C.H. Jan et al., “A 32 nm SoC Platform Technology With 2nd Generation High-k/Metal Gate Transistors,” 2009 IEDM, p. 647.
7. J. Huang et al., “Gate First High-k/Metal Gate Stacks With Zero SiOx Interface Achieving EOT=0.59 nm for 16nm Application,” 2009 Symposium on VLSI Technology.
8. T. Ando, et al., “Understanding Mobility Mechanisms in Extremely Scaled HfO2 (EOT 0.42 nm) Using Remote Interfacial Layer Scavenging Technique and Vt-tuning Dipoles With Gate-First Process,” 2009 IEDM, p. 423.
2010
03/10
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TSMC’s Chiang Sees History on Side of Gate-Last High-k Approach – 2010-02-10 16:40:37 | Semiconductor International

TSMC’s Chiang Sees History on Side of Gate-Last High-k Approach – 2010-02-10 16:40:37 | Semiconductor International.

TSMC’s decision to adopt a gate-last approach to high-k deposition was informed by history, said S.Y. Chiang, in charge of R&D at the foundry. Two decades ago, companies tried to use the same gate electrode for both N- and PMOS transistors, a method that was soon abandoned, Chiang said. After a series of face-to-face meetings, TSMC’s design rules for its high-k process are being accepted by its largest customers.

David Lammers, News Editor — Semiconductor International, 2/10/2010

Last summer, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) made a surprising decision to use a gate-last deposition method for the high-k/metal gate stack of its 28 nm transistors. TSMC’s decision to use a replacement metal gate (RMG) technique was guided by history, said S.Y. Chiang, the senior vice president at TSMC in charge of R&D.

S.Y. Chiang (021010-ShangYiChiang.jpg)S.Y. Chiang, senior vice president, TSMCTwo decades ago, the semiconductor industry went through a similar tussle, when early CMOS developers tried to use an N+ poly gate for both the N-channel and P-channel devices. “When the industry began to do PMOS, companies found an N+ poly gate doesn’t work well,” Chiang said. “It was difficult to lower the Vt, so some people tried to add a counter dopant into the active region of the silicon channel to try to match the Vt. That caused a lot of problems, and made gate control and SCE (short channel effects) much worse.”

The gate-first approach to high-k ran into similar Vt control problems, Chiang said. Efforts to use capping layers improved gate-first performance, but a gate-first cap-layer process “gets very, very complicated and difficult to do,” he said. Two decades ago, for one technology generation, companies also tried to adjust the Vt for both NMOS and PMOS. “We went through exactly the same step when in our history we tried to use N+ poly,” Chiang said.

Asked about the restrictive design rules (RDRs) required for the gate-last method, Chiang said TSMC has been working with the layout teams at its largest customers to adjust to the gate-last high-k flow.

“With the gate-last technology, we do have some restrictions,” he said. “There is difficulty in planarizing it. However, if the layout team is willing to change to a new layout style, then they can get a layout density that is as good as with the gate-first approach. Not better, but the same. And it is not that difficult.” With high-k, Chiang added, “everybody — the process people as well as the layout people — need to adjust the way they do things in order to make the products competitive.”

TSMC’s design services team is working with the layout engineers at its largest customers. Chiang said they have demonstrated that with the appropriate alterations the IP cell libraries can achieve an equivalent layout density as with the gate-first approach. “Some people at first complained a lot, saying there would be a large density gap if they used the TSMC RDRs,” he said. “But after face-to-face meetings, the gate-last technique has been very well accepted.”

TSMC’s customers also appreciate what Chiang said is “a side effect” of using the gate-last approach: higher strain for the PMOS transistors.

TSMC plans to offer its first 28 nm processing by the middle of this year, using an SiON gate stack. “At 28 nm, that is the generation we push oxynitrides to the limit,” Chiang said. “We won’t continue to use oxynitrides after that — the transition has to happen somewhere.” The SiON process does have a cost advantage, and Chiang said customers who are not so concerned about gate leakage can move quickly to the 28 nm generation with the oxynitride process. “When it comes down to leakage, the customers who emphasize gate leakage have got to make the switch to high-k.”

TSMC high-k (021010-TSMCHKMG.jpg)TSMC will use its 28 nm SiON process to shake out issues not related to high-k/metal gate deposition. (Source: TSMC)

After the 28 nm SiON process moves into production at the end of the second quarter, TSMC will work to “clean off” any issues relating to interconnects, contacts, design rules and other issues. “That way, when we offer the HKMG process later in the year, we can be more focused on solving the HKMG process issues,” Chiang said.

Asked if the 28 nm generation promises to be a challenging one, Chiang said, “Some generations are relatively easier. For example, the transition from 90 to 65 nm had a very low risk. I do certainly believe 40 to 28 is very definitely a high-risk one, and we are preparing for that. We are preparing for all the possible scenarios. Reliability is a risk, and yield control. But we are working hard to prepare. Between 2006 and 2009, our headcount doubled, so I am pretty confident we will make this next generation a successful one.”

Chiang predicted the industry will coalesce around the gate-last method. “I do believe the gate-first people will change to gate last at the 22 nm node,” he said. “I am not criticizing them. But I think they will change. Unless they can find some very innovative way to adjust the threshold voltage without a lot of high cost, they will have to change.”

2010
02/11
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Technology@Intel · IEDM, 32nm, and the all new 2010 Intel® Core Processor Family

Technology@Intel · IEDM, 32nm, and the all new 2010 Intel® Core Processor Family.

posted by Kelin Kuhn on January 07, 2010

With today’s launch of the all new 2010 Intel® Core Processor Family (based on Westmere, code name for our 32nm project), this is a great time to discuss the the 32nm process technology (and the semiconductor communities response to this technology!)

Traditionally, Intel presents the details of its process technologies at the International Electron Devices meeting (IEDM) and 32nm is no exception.   Although I was unable to attend the conference this year, my colleagues (and the faithful blogosphere) have provided me with an opportunity to tell the real story.

The 32nm process technology is based on high-k metal gate. Intel was the first manufacturer to introduce the high-k metal gate technology into manufacturing in 45nm (see IEDM 2007) and (as Carl Wintgens from EE times points out) “Semiconductor Insights has yet to observe a metal gate technology in a commercial device from any other semiconductor manufacturer.”

Like Intel’s 45nm technology, Intel’s 32nm high-k metal gate process is a gate-last (or replacement gate process). The gate-last (or replacement gate) architecture provides a higher thermal budget for the midsection (better activation of S/D anneals), lower thermal budget for the metals (improved range of metal choices) AND delivers significant improvement of strain for both NMOS and PMOS.   The metal gate (and associated strain) gives these transistors more performance at the same power, to enable your favorite performance-hungry applications (things like games, video editing and so on).

The high-k metal gate process in 32nm generated some big headlines in the blogsphere. David Lammers of Semiconductor International reported the big news, as “Intel’s flagship 32 nm technology achieved record drive current levels, with the PMOS transistor showing a 35% drive current improvement over the 45 nm PMOS device.” Lammers also picked up a subtle but key aspect of 32nm as he pointed out “For the first time, linear drive currents on the PMOS have overtaken NMOS.” It will only be a short time before saturated drive currents on PMOS overtake NMOS (perhaps at 22nm?).   Matched drive currents on NMOS and PMOS permit the best possible layout density (thus lower cost!) and have been a “wish-list” item from designers for decades.

There has been much discussion on gate first vs gate last (or replacement gate) since Intel’s initial introduction of replacement gate in 45nm. However, as David Lammers from Semiconductor International reports, Intel’s vision on gate last is finally being appreciated. Lammers headline says a great deal with, “Problems with the gate-first approach to high-k/metal gate deposition may force IBM to switch to the gate-last approach pioneered by Intel.” Lammers adds, “Concerns about threshold voltage shifts and other performance problems with the gate-first approach to high-k/metal gate creation may cause GlobalFoundries (Sunnyvale, Calif.) and other members of the IBM-led Fishkill Alliance to shift to a gate-last technique, sources said at the International Electron Devices Meeting (IEDM), going on this week in Baltimore [IEDM 2009].” In addition, Lammers reports, “”The baseline roadmap at TSMC is gate last,” said Jack Sun, in charge of technology strategy at TSMC.”

Of course, the most important point illustrated by 32nm is that it continues to maintain Moore’s law scaling! Carl Wintgens from EE times takes the stance that Moore’s Law is alive an well, with “All three players [i.e. Intel, AMD, TSMC] had comparable critical dimensions, illustrating that Moore’s law is alive and well with no sign of slowing.” Lammers from Semiconductor International was slightly more pessimistic with, “Though several participants at IEDM said CMOS scaling is likely to slow to a three-year pace, Bohr said Intel plans to stay on a two-year cadence.”

As a closing thought, Carl Wintgens from EE times highlights Intel’s continued commitment to driving innovation with “Intel clearly shows leadership in implementing process innovations”

For a look at the detailed IEDM technical papers showcasing these neat features, check out the links below!

32nm at IEDM 2009:  Paper

32nm at IEDM 2008:  Foils and Paper and David Kantor at Real World Technologies 2008 article

2010
01/20
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Technology@Intel · A look at the future of the transistor from the Solid State Devices and Materials Conference (SSDM)

Technology@Intel · A look at the future of the transistor from the Solid State Devices and Materials Conference (SSDM).

A look at the future of the transistor from the Solid State Devices and Materials Conference (SSDM)

posted by Kelin Kuhn on October 30, 2009

I’m writing this on the plane from Narita airport to Portland as I return from  giving the plenary talk at the Solid State Devices and Materials conference (SSDM), in Sendai Japan.  It is always exciting to visit these device conferences to see the myriad of new options that are being discussed for next generation transistors.

Before I get into the technical details, I have a few fun stories to share about my trip.  I arrived a little early, so I could have the weekend to tour Tokyo.  Much of my time in Tokyo was spent figuring out the subway/train system.  In all the excitement, I managed to lose my wallet on the subway, and to my surprise and delight  – it was returned a few hours later (with all the money intact).  I was deeply impressed as I doubt that would happen in New York!   Another adventure was with a Japanese toilet at Tokyo institute of technology. Japanese toilets are quite complicated (among other things, they play music) with a number of interesting features (which I will not describe here, you’ll need to go to Japan to check).  This was one of the more complicated ones, and in looking for the flush button, I pushed a green button that looked reasonable.  Well, it was an alarm button.  A horn sounded, the lights turned on and off and so on and so on.   Made me deeply suspicious of all buttons for the rest of the trip.   At this point, I hoped my adventures were over, but no.    I had a most interesting night on the 12th floor of the hotel when the typhoon Melor passed over (as a side note, I began to feel jinxed, because I ran into Melor a second time when in California a few days later after it had crossed the Pacific).

Anyway, enough of the light stuff, now let’s discuss the meat!   SSDM is a big conference (~1000 people) where the various conference sessions include papers ranging from energy systems to organic semiconductors.   Of the most interest to me were the sessions focusing on the various approaches for continued gate scaling through improved short channel control.

High-k metal gate is the primary path for improved short channel control.  Intel leads the pack in this area, with its recent 32nm announcement demonstrating successful second-generation high-k metal gate (http://www.intel.com/technology/architecture-silicon/32nm/index.htm).  Note that much of the industry is trying to “catch up” to Intel, with significant discussion industry-wide on the correct architecture for the gate (gate-first or replacement, one metal or two, and so on) with representative SSDM papers such as those presented by Drs. Ikeda, Kim and Fukutome.   There is also significant research on gate materials, shown with papers such as those from Drs. Kadoshima and Inumiya.   Another area of strong research is fundamental physics of the HiK-metal gate materials system, with SSDM papers such as those by Drs. Hsieh and Shimizu.

Advanced device architectures are another path for improved short channel control.  This include ultra thin body (UTB) devices, vertical thin body devices (for example, trigate and Finfet), and lateral nanowire devices.   UTB devices are the simplest of the new architectures, with short channel control offered by a thin body, and with fabrication being an extension of historical processing.   An additional advantage of UTB devices is excellent random variation due to the undoped depleted body (several interesting SSDM papers in this area, including the papers of Drs. Andrieu  and Lee).  The problem is that UTB devices are expensive (SOI is NOT cheap), and quite sensitive to variation in the body thickness (changes in body thickness affect VT from quantum effects, and also impact DIBL and SS)).  In addition, the thin body creates high external resistance and makes it extremely difficult to strain the devices.

Multiple gate (MuGFET) devices such as FinFETs or Trigates are a longer term path for improved short channel control.   These devices mitigate many of the variation issues with UTB devices (because the desired fin width is greater than 2X of the equivalent body thickness in an UTB device.) HOWEVER, the non-planarity of these devices represents significant challenges in fabrication.    Dr. Veloso’s paper nicely explored many of these challenges in some detail.    Lateral nanowire devices are next in the logical sequence, again offering significant advantages for short channel control, but at the cost of challenging fabrication.  While nanowires offer further short channel benefit, they have all the issues of FinFETs, along with a host of new issues, many of which were explored in papers from Drs. Chen, Seike, Lee and others.

I had a lot of fun, and learned some new things.   As a wonderful closure for the trip, as we were leaving Narita airport (after pushback and just as the plane started to taxi on its own) all the line service folks (the people who fuel the plane etc.) lined up and waved and then bowed the plane off.  “What a wonderful custom,” I thought, as I waved back.

2010
01/05
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EETimes.com – How much of a lead does Intel have at 32nm? (Dec/09)

EETimes.com – How much of a lead does Intel have at 32nm?.

How much of a lead does Intel have at 32nm?
Carl Wintgens
(12/14/2009 12:01 $ EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=222001158
Intel will soon be releasing their latest processor, code named Westmere, built on 32nm technology. Architecturally, the processor will be similar to the Nehalem design introduced last year and marketed as Core i7. The big change, however, will be Intel’s new 32nm fabrication technology. Semiconductor Insights was fortunate to obtain the desktop version of the processor early and perform an independent detailed analysis of the Westmere/Clarksdale’s process technology. At 32nm, Intel is introducing their second generation of high-k metal gate technology as well as other interesting process innovations. That being said, Semiconductor Insights has yet to observe a metal gate technology in a commercial device from any other semiconductor manufacturer. So, where exactly are Intel’s competitors in the 32nm race?

To this end, let’s compare the two main processor companies, Intel and AMD, and the leading pure-play semiconductor foundry, TSMC. All data presented here was independently gathered by Semiconductor Insights. Since TSMC does not have a product per se, we analyzed devices from a fabless FPGA manufacturer using TSMC technology. FPGA makers are usually among the first adopters of new technology from foundries like TSMC, since smaller geometries allow them to include more logic elements in their product and increase the overall performance and flexibility of their design. Also, note that we did not include the IBM/Common Platform technology due to the limited amount of independent data at this time. However, it will be interesting to see how the relatively new technology alliance will fare in the future against the reigning champion of foundries, TSMC.

To better understand that future, it’s sometimes helpful to look at the past. Table 1 shows the dates of introduction for the 90nm, 65nm, 45nm technology nodes as well as the upcoming 32nm node from our three manufacturers. We can see that Intel has consistently introduced a new process technology at the beginning of the year, every two years. This pace is dictated by Moore’s law, a trend Intel has diligently followed since first observed by Intel’s co-founder, Gordon E. Moore. Intel has been so regular in the launch of new technologies, we can almost safely predict that the next 22nm process from Intel will be ready around the beginning of 2012.

AMD has also stayed on track with Moore’s law for the past tech nodes, introducing new processes during the same year but usually later than Intel. However, a period of more than two years is now expected between the introduction of AMD’s 32nm technology and the previous 45nm node first seen in late 2008. This slowdown may be partly explained by the transfer of AMD’s manufacturing operations to GlobalFoundries but is most likely a sign of how difficult it will be to keep up with Moore’s law beyond the 32nm node.

TSMC’s track record, while not as regular as the two processor companies, depended on the fabless manufacturer’s product roadmap. A three-year gap was observed between the availability of 90nm and 65nm products, followed by an impressive 15-month cycle between 65nm and 45/40nm. With the help of intermediary process nodes slotted in between the major technology nodes, TSMC has been able to launch a new technology approximately every year, setting a rapid pace for the rest of the pure-play foundry industry to follow.


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Moore’s law predicts a 70 percent reduction in the size of the integrated circuit’s features at every technology node. One dimension of interest (besides the gate length of the transistor) is the minimum spacing between interconnect lines. This dimension determines how densely packed the logic gates will be and ultimately how many transistors can fit on a single chip. We plotted (Figure 1 online) the minimum interconnect line pitch for all three manufacturers as a function of the technology node. All three players had comparable critical dimensions, illustrating that Moore’s law is alive and well with no sign of slowing.

Interestingly, TSMC has slightly smaller dimensions than the two other manufacturers, probably because TSMC’s customers are mainly SoC manufacturers, such as graphics processor and FPGA makers. With the latest graphics processors having more than a billion transistors, any reduction in chip size is highly beneficial to foundry clients, even though the individual transistors may not be as fast as Intel’s or AMD’s.

Every new technology node both reduces critical dimensions and improves process. Two fundamental process innovations being adopted by the main semiconductor companies are embedded silicon-germanium source/drain regions (eSiGe) and high-k metal gate technology (HKMG). eSiGe increases the performance of the slower type of transistors (PMOS), while HKMG helps the transistors switch faster and reduces the gate leakage.

Table 2 illustrates when these features were adopted by the three manufacturers. Here, Intel clearly shows leadership in implementing process innovations, having introduced eSiGe first at the 90nm node in 2004. AMD closely follows by one technology node, while TSMC is approximately two generations behind Intel (technically one and a half nodes behind in the case of HKMG since the 28nm node will represent a half-node). Advanced process features, such as silicon-on-insulator (SOI) used by AMD, were not compared if not widely adopted.

In the end, a better process technology does not guarantee a better semiconductor. In the past, AMD mitigated the lag in process and gained market share from Intel by making sound circuit design decisions such as having an efficient, short pipeline architecture and the first integrated memory controller on-die (later implemented by Intel). Intel is also facing tough competition in other market segments such as graphics processing and in the fast-growing ultra-low-power device market. However, assuming comparable designs, Intel’s technology lead will likely allow it to have an edge over the competition, at least until the introduction of the 32nm technology from AMD/GlobalFoundries in late 2010 or early 2011.


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2010
01/01
CATEGORY
Intel
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