Posts Tagged ‘ 16nm ’

EETimes.com – Intel’s Gargini pushes III-V-on-silicon as 2015 transistor option

EETimes.com – Intel’s Gargini pushes III-V-on-silicon as 2015 transistor option.

LONDON — A presentation prepared by Paolo Gargini, Intel’s director of technology strategy, to give to the Industry Strategy Symposium Europe, held in Dublin, Ireland, earlier this week, stressed Intel’s progress in adding compound semiconductor layers to silicon as a means of continuing scaling and reducing power consumption.

Gargini, also chairman of the International Technology Roadmap for Semiconductors (ITRS), said in the presentation that the inclusion of III-V materials is a 2015 transistor option that could deliver either three times the performance of silicon at the same power consumption, or deliver the same performance as silicon at one-tenth the power consumption. However, integration of a thin compound semiconductor transistor channel with conventional silicon manufacturing would be the key to adoption.

While exceptional progress has been made in silicon to get to 32-nm, Gargini indicated in his slides that progress is coming only with more and more complicated additions to the basic silicon manufacturing process, such as the increased amounts of strain necessary to increase the electron mobility above its natural value; and the possible use of 3-D structures such as FinFETs.

Multigate FinFETs have advantages in improved electrostatics and a steeper sub-threshold slope, but Gargini put question marks against such things as parasitic resistance and capacitance and a layout methodology.

“Increase mobility in the transistor channel leads to higher performance and less energy consumption,” said Gargini on the slide, adding, “compound semiconductors have higher electron mobility than silicon; indium antimonide is highest of all.” Where gallium arsenide has 8 times higher mobility than silicon, indium arsenide is 33 times higher and indium antimonide is 50 times higher.

In the presentation Gargini laid out a few alternatives for integration. One method would be to include indium antimonide quantum-well FETs on a semi-insulating gallium arsenide substrate. Both depletion- and enhancement mode devices are possible.

As an alternative Gargini outlined progress in integrating an InGaAs quantum-well FET with a high-k dielectric gate stack. Gargini highlighted a series of papers presented by Marko Radosavljevic of Intel to the International Electron Devices Meeting (IEDM) over the years 2007 to 2009. This illustrated progress in developing the NMOS, PMOS transistors and, in December 2009, the high-K metal gate.

Gargini’s final conclusion was: “The advancement in non-silicon semiconductors deposited on silicon substrates could enable a new family of low power devices in the future.”

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Nano-injection; NGL to make 0.039um2 bitcell for 16nm

  • 나노 인젝션(NanoInjection)이라는 새로운 리소그래피 기술을 이용한다. 이는 가스를 불어 넣는 지점에 전자 빔을 대서 패턴을 그리는방법이다(그림6(b)).
  • 나노 인젝션의 이점은 기존의 전자 빔 리소그래피 기술과는 달리 포토 레지스트가 필요 없다는 점이다. 포토 레지스트를 쓰지 않아도 되기 때문에 리소그래피의 해상도를 높이기 쉽고, 결과적으로 미세한 패턴을 형성할 수 있게 되는 것이다.
  • 하지만 단점도 있다. 기존의 전자 빔 기술 등과 마찬가지로 생산성이 낮다는 것이다. 앞으로 생산성 향상을 위한 연구개발이 진행될 것으로 보인다.
  • Nano injection lithography eliminates the masks of other lithography techniques. Eliminating the masks and the photoresist cuts the patterning process from five steps to one, greatly simplifying production.
  • A new type of lithography, which uses an electron beam to spark a chemical reaction, could provide a cheaper way to build the incredibly tiny transistors that the chipmaking industry will require in a few years.
  • Researchers from Taiwan and the University of California, Berkeley, say they’ve made static random access memory (SRAM) that anticipates 16-nanometer chip features with a new process called nano injection lithography.
  • They say their technique may provide an alternative to lithography that relies on extreme ultraviolet light (EUV), which still is beset by problems and could be extremely expensive.
  • a metallorganic gas, an organic molecule studded with atoms of platinum.
  • An electron beam with a diameter of 4.6 nm is fired at the gas, causing a chemical reaction that deposits the platinum on the silicon chip in the desired pattern, while the rest of the gas flows away.
  • With this hard mask deposited on the silicon, the researchers then use chemicals to etch away exposed silicon and thereby create the desired circuits. The platinum mask is then chemically removed.